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ZL50110/11/14 128, 256 and 1024 Channel CESoP Processors
Data Sheet Features
General * * * Circuit Emulation Services over Packet (CESoP) transport for MPLS, IP and Ethernet networks On chip timing & synchronization recovery across a packet network Grooming capability for Nx64 Kbps trunking * *
ZL50110GAG ZL50111GAG ZL50114GAG
October 2005
Ordering Information
552 PBGA 552 PBGA 552 PBGA Trays, Bake & Drypack Trays, Bake & Drypack Trays, Bake & Drypack
-40C to +85C Direct connection to LIUs, framers, backplanes Dual reference Stratum 3, 4 and 4E DPLL for synchronous operation
Circuit Emulation Services * * * * * Complies with ITU-T recommendation Y.1413 Complies with IETF PWE3 draft standards for CESoPSN and SAToP Complies with CESoP draft IAs for MEF and MFA Structured, synchronous CESoP with clock recovery Unstructured, asynchronous CESoP, with integral per stream clock recovery
Network Interfaces * Up to 3 x 100 Mbps MII Fast Ethernet or Dual Redundant 1000 Mbps GMII/TBI Ethernet Interfaces
System Interfaces * * * Flexible 32 bit host CPU interface (Motorola PowerQUICCTM compatible) On-chip packet memory for self-contained operation, with buffer depths of over 16 ms Up to 8 Mbytes of off-chip packet memory, supporting buffer depths of over 128 ms
TDM Interfaces * * * Up to 32 T1/E1, 8 J2, 2 T3/E3 or 1 STS-1 ports H.110, H-MVIP, ST-BUS backplanes Up to 1024 bi-directional 64 Kbps channels
32 T1/E1, 8 J2, 2 T3/E3 or 1 STS-1 ports H.110, H-MVIP, ST-BUS backplanes
TDM Interface
(LIU, Framer, Backplane)
Multi-Protocol Packet Processing Engine
PW, RTP, UDP, IPv4, IPv6, MPLS, ECID, VLAN, User Defined, Others
Triple Packet Interface MAC
(MII, GMII, TBI)
Per Port DCO for Clock Recovery
On Chip Packet Memory
Backplane Clocks
(Jitter Buffer Compensation for 16-128 ms of Packet Delay Variation) Dual Reference Stratum 3 DPLL Host Processor Interface External Memory Interface (optional)
32-bit Motorola compatible DMA for signaling packets
ZBT-SRAM (0 - 8 Mbytes)
Figure 1 - ZL50110/11/14 High Level Overview 1
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
Triple 100 Mbps MII Fast Ethernet or Dual Redudnat 1000 Mbps GMII/ TBI Gigabit Ethernet
ZL50110/11/14
Packet Processing Functions * * * * *
Data Sheet
Flexible, multi-protocol packet encapsulation including IPv4, IPv6, RTP, MPLS, L2TPv3, ITU-T Y.1413., IETF CESoPSN, IETF SAToP and user programmable Packet re-sequencing to allow lost packet detection Four classes of service with programmable priority mechanisms (WFQ and SP) using egress queues Flexible classification of incoming packets at layers 2, 3, 4, and 5 Supports up to 128 separate CESoP connections across the Packet Switched Network
Applications
* Circuit Emulation Services over Packet Networks * * * * * * * Leased Line support over packet networks Multi-Tenant Unit access concentration TDM over Cable Fibre To The Premises G/E-PON Layer 2 VPN services
Customer-premise and Provider Edge Routers and Switches Packet switched backplane applications
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Zarlink Semiconductor Inc.
ZL50110/11/14
Description
Data Sheet
The ZL50110/11/14 family of CESoP processors are highly functional TDM to Packet bridging devices. The ZL50110/11/14 provides both structured and unstructured circuit emulation services over packet (CESoP) for up to 32 T1, 32 E1 and 8 J2 streams across a packet network based on MPLS, IP or Ethernet. The ZL50111 also supports unstructured T3, E3 and STS-1 streams. The circuit emulation features in the ZL50110/11/14 family comply with the ITU Recommendation Y.1413, as well as the emerging CESoP standards from the Metro Ethernet Forum (MEF) and MPLS and Frame Relay Alliance (MFA). The ZL50110/11/14 also complies with the standards currently being developed within the IETF's PWE3 working group, listed below. * * Structure-Agnostic TDM over Packet (SAToP) - draft-ietf-pwe3-satop Structure-aware TDM Circuit Emulation Service over Packet Switched Network (CESoPSN) - draft-ietfpwe3-cesopsn
The ZL50110/11/14 provides up to triple 100 Mbps MII ports or dual redundant 1000 Mbps GMII/TBI ports. The ZL50110/11/14 incorporates a range of powerful clock recovery mechanisms for each TDM stream, allowing the frequency of the source clock to be faithfully generated at the destination, enabling greater system performance and quality. Timing is carried using RTP or similar protocols, and both adaptive and differential clock recovery schemes are included, allowing the customer to choose the correct scheme for the application. An externally supplied clock may also be used to drive the TDM interface of the ZL50110/11/14. The ZL50110/11/14 incur very low latency for the data flow, thereby increasing QoS when carrying voice services across the Packet Switched Network. Voice, when carried using CESoP, which typically has latencies of less than 10 ms, does not require expensive processing such as compression and echo cancellation. The ZL50110/11/14 is capable of assembling user-defined packets of TDM traffic from the TDM interface and transmitting them out the packet interfaces using a variety of protocols. The ZL50110/11/14 supports a range of different packet switched networks, including Ethernet VLANs, IP (both versions 4 and 6) and MPLS. The devices also supports four different classes of service on packet egress, allowing priority treatment of TDM-based traffic. This can be used to help minimize latency variation in the TDM data. Packets received from the packet interfaces are parsed to determine the egress destination, and are appropriately queued to the TDM interface, they can also be forwarded to the host interface, or back toward the packet interface. Packets queued to the TDM interface can be re-ordered based on sequence number, and lost packets filled in to maintain timing integrity. The ZL50110/11/14 family includes sufficient on-chip memory that external memory is not required in most applications. This reduces system costs and simplifies the design. For applications that do require more memory (e.g., high stream count or high latency), the device supports up to 8 Mbytes of SSRAM. A comprehensive evaluation system is available upon request from your local Zarlink representative or distributor. This system includes the CESoP processor, various TDM interfaces and a fully featured evaluation software GUI that will run on a Windows PC.
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Zarlink Semiconductor Inc.
ZL50110/11/14
Device Line Up
Data Sheet
There are three products within the ZL50110/11/14 family, with capacity as shown in the following table: Device ZL50114 TDM Interfaces 4 T1, 4 E1, or 1 J2 streams or 4 MVIP/ST-BUS streams at 2.048 Mbps or 1 H.110/H-MVIP/ST-BUS streams at 8.192 Mbps 8 T1, 8 E1 or 2 J2 streams or 8 MVIP/ST-BUS streams at 2.048 Mbps or 2 H.110/H-MVIP/ST-BUS streams at 8.192 Mbps 32 T1, 32 E1, 8 J2, 2 T3, 2 E3 or 1 STS-1 streams or 32 MVIP/ST-BUS streams at 2.048 Mbps or 8 H.110/H-MVIP/ST-BUS streams at 8.192 Mbps Ethernet Packet I/F Dual 100 Mbps MII or Dual Redundant 1000 Mbps GMII/TBI Dual 100 Mbps MII or Dual Redundant 1000 Mbps GMII/TBI Triple 100 Mbps MII or Dual Redundant 1000 Mbps GMII/TBI or Single 100 Mbps MII and Single 1000 Mbps GMII/TBI
ZL50110
ZL50111
Table 1 - Capacity of Devices in the ZL50110/11/14 Family
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Zarlink Semiconductor Inc.
ZL50110/11/14 Table of Contents
Data Sheet
1.0 Changes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.0 Physical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.0 External Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 TDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1.1 ZL50111 Variant TDM Stream Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1.2 ZL50110 Variant TDM stream connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1.3 ZL50114 Variant TDM Stream Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.4 TDM Signals Common to ZL50111, ZL50110 and ZL50114 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2 PAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.3 Packet Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.4 External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.5 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.6 System Function Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.7 Test Facilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.7.1 Administration, Control and Test Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.7.2 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.8 Miscellaneous Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.9 Power and Ground Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.10 Internal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.0 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.1 Leased Line Provision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.2 Metropolitan Area Network Aggregation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.3 Digital Loop Carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.4 Remote Concentrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.5 Cell Site Backhaul . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.6 Metro Ethernet Equipment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.2 Data and Control Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3 TDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.3.1 TDM Interface Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.3.2 Structured TDM Port Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.3.3 TDM Clock Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.3.3.1 Synchronous TDM Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.3.3.2 Asynchronous TDM Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.4 Payload Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.4.1 Structured Payload Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.4.1.1 Structured Payload Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.4.2 Unstructured Payload Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.5 Protocol Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.6 Packet Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.7 TDM Formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.0 Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.1 Differential Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.2 Adaptive Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3 SYSTEM_CLK Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.0 System Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.1 Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.2 Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.3 Host Packet Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.4 Loss of Service (LOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
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ZL50110/11/14 Table of Contents
Data Sheet
7.5 External Memory Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.6 GIGABIT Ethernet - Recommended Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.6.1 Central Ethernet Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.6.2 Redundant Ethernet Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.7 Power Up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.8 JTAG Interface and Board Level Test Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.9 External Component Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.10 Miscellaneous Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.11 Test Modes Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.11.1.1 System Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.11.1.2 System Tri-State Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.11.2 Test Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.11.3 System Normal Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.11.4 System Tri-state Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 8.0 DPLL Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8.1.1 Locking Mode (normal operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8.1.2 Holdover Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 8.1.3 Freerun Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 8.1.4 Powerdown Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 8.2 Reference Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 8.3 Locking Mode Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 8.4 Locking Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 8.5 Locking Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 8.6 Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.7 Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.7.1 Acceptance of Input Wander . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.7.2 Intrinsic Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.7.3 Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.7.4 Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 8.8 Maximum Time Interval Error (MTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 9.0 Memory Map and Register Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.0 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.0 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.1 TDM Interface Timing - ST-BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.1.1 ST-BUS Slave Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.1.2 ST-BUS Master Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11.2 TDM Interface Timing - H.110 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11.3 TDM Interface Timing - H-MVIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 11.4 TDM LIU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 11.5 PAC Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 11.6 Packet Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 11.6.1 MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 11.6.2 MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 11.6.3 GMII Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.6.4 GMII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 11.6.5 TBI Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 11.6.6 Management Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 11.7 External Memory Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 11.8 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 11.9 System Function Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
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11.10 JTAG Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 12.0 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 13.0 Design and Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 13.1 High Speed Clock & Data Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 13.1.1 External Memory Interface - special considerations during layout. . . . . . . . . . . . . . . . . . . . . . . . . 95 13.1.2 GMAC Interface - special considerations during layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.1.3 TDM Interface - special considerations during layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.1.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.2 CPU TA Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.3 Mx_LINKUP_LED Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 14.0 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 14.1 External Standards/Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 14.2 Zarlink Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 15.0 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
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Figure 1 - ZL50110/11/14 High Level Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - ZL50111 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 3 - ZL50110 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 4 - ZL50114 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 5 - Leased Line Services Over a Circuit Emulation Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 6 - Metropolitan Area Network Aggregation using CESoP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 7 - Digital Loop Carrier using CESoP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 8 - Remote Concentrator using CESoP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 9 - Cell Site Backhaul using CESoP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 10 - Metro Ethernet Equipment using CESoP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 11 - ZL50110/11/14 Family Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 12 - ZL50110/11/14 Data and Control Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 13 - Synchronous TDM Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 14 - ZL50110/11/14 Packet Format - Structured Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 15 - Channel Order for Packet Formation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 16 - ZL50110/11/14 Packet Format - Unstructured Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 17 - Differential Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 18 - Adaptive Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 19 - External Memory Requirement for ZL50111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 20 - External Memory Requirement for ZL50110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 21 - Gigabit Ethernet Connection - Central Ethernet Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 22 - Gigabit Ethernet Connection - Redundant Ethernet Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 23 - Powering Up the ZL50110/11/14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 24 - Jitter Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 25 - Jitter Transfer Function - Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 26 - TDM ST-BUS Slave Mode Timing at 8.192 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 27 - TDM ST-BUS Slave Mode Timing at 2.048 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 28 - TDM Bus Master Mode Timing at 8.192 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 29 - TDM Bus Master Mode Timing at 2.048 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 30 - H.110 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 31 - TDM - H-MVIP Timing Diagram for 16 MHz Clock (8.192 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 32 - TDM-LIU Structured Transmission/Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 33 - MII Transmit Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 34 - MII Receive Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 35 - GMII Transmit Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 36 - GMII Receive Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 37 - TBI Transmit Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 38 - TBI Receive Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 39 - Management Interface Timing for Ethernet Port - Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 40 - Management Interface Timing for Ethernet Port - Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 41 - External RAM Read and Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 42 - CPU Read - MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Figure 43 - CPU Write - MPC8260. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Figure 44 - CPU DMA Read - MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure 45 - CPU DMA Write - MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure 46 - JTAG Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Figure 47 - JTAG Clock and Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Figure 48 - ZL50110/11/14 Power Consumption Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
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Figure 49 - CPU_TA Board Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Figure 50 - Mx_LINKUP_LED Stuffing Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
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Table 1 - Capacity of Devices in the ZL50110/11/14 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 2 - TDM Interface ZL50111 Stream Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 3 - TDM Interface ZL50110 Stream Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 4 - TDM Interface ZL50114 Stream Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 5 - TDM Interface Common Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 6 - PAC Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 7 - Packet Interface Signal Mapping - MII to GMII/TBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 8 - MII Management Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 9 - MII Port 0 Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 10 - MII Port 1 Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 11 - MII Port 2 Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 12 - MII Port 3 Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 13 - External Memory Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 14 - CPU Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 15 - System Function Interface Package Ball Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 16 - Administration/Control Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 17 - JTAG Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 18 - Miscellaneous Inputs Package Ball Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 19 - Power and Ground Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 20 - No Connection Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 21 - Standard Device Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 22 - TDM Services Offered by the ZL50110/11/14 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 23 - Some of the TDM Port Formats Accepted by the ZL50110/11/14 Family . . . . . . . . . . . . . . . . . . . . . . . 51 Table 24 - DMA Maximum Bandwidths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 25 - Test Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 26 - DPLL Input Reference Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 27 - TDM ST-BUS Master Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 28 - TDM H.110 Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 29 - TDM H-MVIP Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 30 - TDM - LIU Structured Transmission/Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 31 - PAC Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 32 - MII Transmit Timing - 100 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 33 - MII Receive Timing - 100 Mbps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 34 - GMII Transmit Timing - 1000 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 35 - GMII Receive Timing - 1000 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 36 - TBI Timing - 1000 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 37 - MAC Management Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 38 - External Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 39 - CPU Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 40 - System Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 41 - JTAG Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 42 - Mx_LINKUP_LED Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 43 - Mx_LINKUP_LED Stuffing Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
10
Zarlink Semiconductor Inc.
ZL50110/11/14
1.0 Changes Summary
Data Sheet
The following table captures the changes from the April 2005 issue. Page Item Change Clarified ZL50111 supports 3 MII ports, ZL50110/4 support 2 MII ports. 41, 42 57 Section 3.6 and Section 3.7.2 Section 6.3 Added external pull-up/pull-down resistor recommendations for SYSTEM_RST, SYSTEM_DEBUG, JTAG_TRST, JTAG_TCK. Added Section 6.3 SYSTEM_CLK Considerations.
The following table captures the changes from the January 2005 issue. Page Item Change Clarified data sheet to indicate ZL5011x supports clock recovery in both synchronous and asynchronous modes of operation. 89 Figure 44 Inverted polarity of CPU_DREQ0 and CPU_DREQ1 to conform with default MPC8260. Polarity of CPU_DREQ and CPU_SDACK remains programmable through API. Inverted polarity of CPU_DREQ0 and CPU_DREQ1 to conform with default MPC8260. Polarity of CPU_DREQ and CPU_SDACK remains programmable through API.
89
Figure 45
The following table captures the changes from the October 2004 issue. Page 42 Section 3.7.1 Item Change Added 5 kohm pulldown recommendation to GPIO signals.
The following table captures the changes from the September 2004 issue. Page 12, 16, 19 73 98 Item Fig. 2 and Ball Signal Assignment Table DC Electrical Characteristics Table and Output Levels Table Section 13.3 Change Corrected Mx_LINKUP_LED pin assignment. Changed Electrical Characteristics to differentiate between 3.3 V and 5 V tolerant signals. New section added; Mx_LINKUP_LED Outputs.
11
Zarlink Semiconductor Inc.
ZL50110/11/14
2.0 Physical Specification
Data Sheet
The ZL50111 will be packaged in a PBGA device. Features: * * * * * * Body Size: Ball Count: Ball Pitch: Ball Matrix: Ball Diameter: Total Package Thickness: 35 mm x 35 mm (typ) 552 1.27 mm (typ) 26 x 26 0.75 mm (typ) 2.33 mm (typ)
The ZL50110 will be packaged in a PBGA device. Features: * * * * * * Body Size: Ball Count: Ball Pitch: Ball Matrix: Ball Diameter: Total Package Thickness: 35 mm x 35 mm (typ) 552 1.27 mm (typ) 26 x 26 0.75 mm (typ) 2.33 mm (typ)
The ZL50114 will be packaged in a PBGA device. Features: * * * * * * Body Size: Ball Count: Ball Pitch: Ball Matrix: Ball Diameter: Total Package Thickness: 35 mm x 35 mm (typ) 552 1.27 mm (typ) 26 x 26 0.75 mm (typ) 2.33 mm (typ)
12
Zarlink Semiconductor Inc.
ZL50110/11/14
ZL50111 Package view from TOP side. Note that ball A1 is non-chamfered corner
Data Sheet
12 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
GND
3456
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
GND TDM_STo[ TDM_STo[ TDM_CLK TDM_STo[ TDM_CLK TDM_STi[ TDM_CLKi TDM_STi[ TDM_STo[ TDM_STi[ TDM_CLK TDM_CLK 13] 14] o[15] 16] o[18] 18] [20] 20] 21] 21] o[24] o[25] GND
TDM_STo[ TDM_CLK TDM_STo[ TDM_STo[ TDM_STi[ TDM_STo[ TDM_STi[ TDM_CLK TDM_CLKiTDM_CLKi TDM_CLK 1] o[3] 4] 5] 6] 7] 7] o[10] [10] [11] o[13]
TDM_FRM TDM_STo[ TDM_STi[ TDM_CLKi TDM_STi[ TDM_CLK TDM_STo[ TDM_CLK TDM_CLKi TDM_STo[ TDM_STi[ TDM_CLKi TDM_STo[ TDM_STi[ TDM_CLKi TDM_STi[ TDM_STi[ TDM_CLKi TDM_CLK TDM_STo[ TDM_STo[ TDM_CLK TDM_STo[ TDM_CLK TDM_STi[ TDM_CLK o_REF 0] 2] [3] 4] o[6] 6] o[8] [9] 10] 10] [12] 12] 13] [15] 15] 17] [18] o[20] 19] 22] o[23] 24] o[26] 24] o[27]
TDM_CLKiTDM_FRMTDM_CLKi TDM_CLK TDM_STi[ TDM_CLK TDM_CLKi TDM_CLKi TDM_CLK TDM_STo[ TDM_STi[ TDM_STi[ TDM_CLKi TDM_CLK TDM_CLK TDM_STi[ TDM_CLK TDM_STi[ TDM_CLK TDM_CLKiTDM_CLKi TDM_STi[ TDM_STo[ TDM_CLKi TDM_STi[ TDM_STi[ P i_REF _REF o[1] 3] o[2] [6] [7] o[9] 9] 9] 11] [13] o[14] o[16] 16] o[17] 19] o[21] [21] [24] 22] 26] [27] 27] 28]
RAM_DAT RAM_DAT TDM_CLKi RAM_DAT TDM_STi[ TDM_CLKi TDM_STo[ TDM_STi[ TDM_CLKi TDM_CLK TDM_STi[ TDM_CLK TDM_STi[ TDM_STi[ TDM_CLKi TDM_CLK TDM_STo[ TDM_STo[ TDM_CLK TDM_STo[ TDM_STo[ TDM_CLKi TDM_CLK TDM_CLKi TDM_STi[ TDM_STi[ A[3] A[1] S A[0] 0] [1] 3] 5] [5] o[7] 8] o[11] 12] 14] [16] o[19] 18] 20] o[22] 27] 25] [26] o[28] [29] 29] 31]
RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT TDM_CLK TDM_CLKi TDM_CLK TDM_STi[ TDM_CLKi TDM_STo[ TDM_CLKi TDM_CLK TDM_STo[ TDM_CLKi TDM_CLKi TDM_STo[ TDM_STi[ TDM_CLKi TDM_STi[ TDM_CLKi A[10] A[9] A[5] A[4] A[2] o_REF [0] o[4] 1] [4] 8] [8] o[12] 15] [17] [19] 23] 23] [25] 26] [28]
GND
TDM_CLK TDM_CLKi TDM_STi[ TDM_STo[ o[30] [30] 30] 29]
RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT A[15] A[13] A[12] A[6] A[7]
GND
VDD_COR TDM_STo[ TDM_CLK TDM_CLKi TDM_CLK VDD_COR TDM_STo[ TDM_CLKiVDD_COR TDM_STo[ TDM_CLKi TDM_STi[ TDM_CLKi VDD_COR E 2] o[0] [2] o[5] E 11] [14] E 17] [22] 25] [23] E
GND
TDM_CLKi TDM_CLK TDM_STo[ TDM_CLK M1_LINKU [31] o[29] 28] o[31] P_LED
RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT A[21] A[18] A[16] A[14] A[11] A[8]
TDM_STo[ TDM_STo[ M2_LINKUM3_LINKU M1_GIGA M_MDIO 31] 30] P_LED P_LED BIT_LED
RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT VDD_COR A[25] A[24] A[23] A[19] A[17] E
VDD_COR M0_GIGA M_MDC E BIT_LED
M3_CRS M3_TXCL M3_RXER K
RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT A[29] A[28] A[27] A[26] A[22] A[20]
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
M3_RXDV M3_RXD[3M3_RXD[2M3_RXD[1 M3_RXD[0 M3_COL ] ] ] ]
RAM_PAR RAM_PAR RAM_DAT RAM_DAT ITY[1] ITY[0] A[31] A[30]
GND
VDD_COR E
VDD_IO
VDD_IO
VDD_COR E
GND
M3_TXD[3 M3_TXEN M3_TXER M3_RXCL ] K
RAM_PAR RAM_PAR RAM_PAR RAM_PAR RAM_PAR RAM_PAR ITY[7] ITY[6] ITY[5] ITY[4] ITY[3] ITY[2]
VDD_IO
GND
GND
GND
GND
GND
GND
VDD_IO
M1_RXER M1_TXCL M1_CRS M3_TXD[0 M3_TXD[1 M3_TXD[2 K ] ] ]
RAM_ADD RAM_ADD RAM_ADD RAM_ADD RAM_ADD RAM_ADD R[5] R[4] R[2] R[3] R[0] R[1]
VDD_IO
GND
GND
GND
GND
GND
GND
VDD_IO
VDD_COR M1_REFC M1_RXCL M1_RXD[5 M1_RXD[7 M1_RXDV E LK K ] ]
GND
RAM_ADD RAM_ADD RAM_ADD R[6] R[7] R[8]
GND
VDD_COR E
VDD_IO
GND
GND
GND
GND
GND
GND
VDD_IO
M1_GTX_ CLK
GND
M1_TXER M1_RXD[2 M1_RXD[3 ] ]
GND
RAM_ADD RAM_ADD RAM_ADD RAM_ADD RAM_ADD R[9] R[10] R[11] R[13] R[16]
GND
VDD_IO
GND
GND
GND
GND
GND
GND
VDD_IO
M1_TXD[2 M1_TXD[6 M1_TXEN ] ]
GND
M1_RXD[4 M1_RXD[6 ] ]
RAM_ADD RAM_ADD RAM_ADD RAM_ADD IC_GND R[12] R[14] R[15] R[19]
IC
VDD_IO
GND
GND
GND
GND
GND
GND
VDD_IO
M1_TXD[0 M1_TXD[3 M1_TXD[5 M1_TXD[7 M1_COL M1_RXD[1 ] ] ] ] ]
RAM_ADD RAM_ADD RAM_BW IC_GND R[17] R[18] _B
GND
A1VDD
VDD_IO
GND
GND
GND
GND
GND
GND
VDD_IO
VDD_COR M1_TXD[1 M1_TXD[4 E ] ]
GND
M1_RBC1 M1_RXD[0 ]
PLL_PRI RAM_BW RAM_BW RAM_RW SYSTEM_ SYSTEM_ _A _C DEBUG CLK
VDD_IO
VDD_IO
M0_GTX_ M0_RXD[2M0_RXD[5 M0_TXCL M0_CRS M1_RBC0 CLK ] ] K
PLL_SEC RAM_BW RAM_BW SYSTEM_ GPIO[2] VDD_COR _D _F RST E
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
M0_TXD[7 M0_TXER M0_TXEN M0_RXD[4 M0_RXDV M0_RXER ] ]
RAM_BW RAM_BW GPIO[0] _E _G
GPIO[3]
GPIO[9] RAM_DAT A[33]
M0_TXD[2 M0_TXD[5 M0_TXD[6 M0_RXD[6 M0_RXD[7 M0_RXD[3 ] ] ] ] ] ]
RAM_BW GPIO[4] _H
GPIO[6]
GPIO[10] RAM_DAT VDD_COR A[32] E
VDD_COR M0_TXD[1 M0_TXD[4 M0_RBC0 M0_COL M0_RXD[1 E ] ] ]
GPIO[1]
GPIO[7]
GPIO[8]
GPIO[15] RAM_DAT A[39]
GND
RAM_DAT RAM_DAT VDD_COR JTAG_TM CPU_ADD CPU_ADD VDD_COR VDD_COR CPU_DAT CPU_DAT CPU_DAT VDD_COR M2_RXCL M2_RXDV A[45] A[52] E S R[2] R[12] E E A[8] A[15] A[23] E K
GND
M0_TXD[0 M0_TXD[3 M0_REFC M0_RBC1 M0_RXD[0 ] ] LK ]
GPIO[5]
GPIO[11] GPIO[14] RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT TEST_MO A[38] A[43] A[44] A[51] A[60] DE[1]
GND
CPU_ADD CPU_ADD CPU_ADD CPU_TA CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT M2_TXER M2_RXD[1 M0_RXCL M0_LINKUM2_ACTIV M1_ACTIV M3_ACTIV R[6] R[14] R[23] A[1] A[7] A[12] A[22] A[30] ] K P_LED E_LED E_LED E_LED
GPIO[12] GPIO[13] RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT TEST_MO JTAG_TD CPU_ADD CPU_ADD CPU_ADD CPU_ADD CPU_CLK CPU_DRE A[37] A[42] A[46] A[49] A[59] DE[0] O R[4] R[9] R[16] R[22] Q0
IC
CPU_DAT CPU_DAT CPU_DAT CPU_DAT M2_TXD[1 M2_TXEN M2_RXD[2 M2_RXER M2_CRS M0_ACTIV A[10] A[16] A[21] A[27] ] ] E_LED
RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT JTAG_TC IC-GND CPU_ADD CPU_ADD CPU_ADD CPU_ADD CPU_WE CPU_SDA CPU_IRE CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT M2_TXD[2 M2_RXD[0 M2_RXD[3 M2_TXCL A[34] A[36] A[41] A[47] A[53] A[58] A[63] K R[7] R[11] R[17] CK2 Q1 A[3] A[6] A[14] A[20] A[24] A[29] ] ] ] K R[21]
RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT JTAG_TR IC_GND CPU_ADD CPU_ADD CPU_ADD CPU_ADD CPU_ADD CPU_OE CPU_TS_ CPU_DRE A[35] A[40] A[48] A[54] A[57] A[62] ST R[3] R[8] R[13] R[18] R[20] ALE Q1
IC
CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT M2_TXD[0 M2_TXD[3 M2_COL A[4] A[9] A[13] A[18] A[25] A[28] ] ]
GND
RAM_DAT RAM_DAT RAM_DAT RAM_DAT TEST_MO JTAG_TDI IC_GND CPU_ADD CPU_ADD CPU_ADD CPU_ADD A[50] A[55] A[56] A[61] DE[2] R[5] R[10] R[15] R[19]
GND
CPU_CS CPU_SDA IC_VDD_I CPU_IRE CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CK1 O Q0 A[0] A[5] A[2] A[11] A[17] A[19] A[26] A[31]
GND
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
12
3456
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Figure 2 - ZL50111 Package View and Ball Positions
13
Zarlink Semiconductor Inc.
ZL50110/11/14
ZL50110 Package view from TOP side. Note that ball A1 is non-chamfered corner.
Data Sheet
12 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
GND
3456
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
N/C N/C N/C N/C GND N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C GND N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C
TDM_STo TDM_CL TDM_STo TDM_STo TDM_STi[ TDM_STo TDM_STi[ [1] Ko[3] [4] [5] 6] [7] 7]
TDM_FR TDM_STo TDM_STi[ TDM_CL TDM_STi[ TDM_CL TDM_STo Mo_REF [0] 2] Ki[3] 4] Ko[6] [6]
TDM_CL TDM_FR TDM_CL TDM_CL TDM_STi[ TDM_CL TDM_CL TDM_CL KiP Mi_REF Ki_REF Ko[1] 3] Ko[2] Ki[6] Ki[7]
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
RAM_DA RAM_DA TDM_CL RAM_DA TDM_STi[ TDM_CL TDM_STo TDM_STi[ TDM_CL TDM_CL TA[3] TA[1] KiS TA[0] 0] Ki[1] [3] 5] Ki[5] Ko[7] RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA TDM_CL TDM_CL TDM_CL TDM_STi[ TDM_CL TA[10] TA[9] TA[5] TA[4] TA[2] Ko_REF Ki[0] Ko[4] 1] Ki[4] RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA TA[15] TA[13] TA[12] TA[6] TA[7] GND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
GND
N/C
N/C
N/C
N/C
VDD_CO TDM_STo TDM_CL TDM_CL TDM_CL VDD_CO RE [2] Ko[0] Ki[2] Ko[5] RE
N/C
N/C
VDD_CO RE
N/C
N/C
N/C
N/C
VDD_CO RE
GND
N/C
N/C
N/C
N/C
N/C
RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA TA[21] TA[18] TA[16] TA[14] TA[11] TA[8] RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA VDD_CO TA[25] TA[24] TA[23] TA[19] TA[17] RE RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA TA[29] TA[28] TA[27] TA[26] TA[22] TA[20] RAM_PA RAM_PA RAM_DA RAM_DA RITY[1] RITY[0] TA[31] TA[30] GND VDD_CO RE VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO
N/C
N/C
M1_LINK M0_LINK M1_GIGA M_MDIO UP_LED UP_LED BIT_LED N/C N/C N/C
VDD_CO M0_GIGA M_MDC RE BIT_LED N/C N/C N/C
N/C
N/C
N/C
VDD_IO
VDD_IO
VDD_CO RE
GND
N/C
N/C
N/C
N/C
RAM_PA RAM_PA RAM_PA RAM_PA RAM_PA RAM_PA RITY[7] RITY[6] RITY[5] RITY[4] RITY[3] RITY[2] RAM_AD RAM_AD RAM_AD RAM_AD RAM_AD RAM_AD DR[5] DR[4] DR[2] DR[3] DR[0] DR[1] GND RAM_AD RAM_AD RAM_AD DR[6] DR[7] DR[8] GND VDD_CO RE GND
VDD_IO
GND
GND
GND
GND
GND
GND
VDD_IO
M1_RXE M1_TXCL M1_CRS R K
N/C
N/C
N/C
VDD_IO
GND
GND
GND
GND
GND
GND
VDD_IO
VDD_CO M1_REF M1_RXCL M1_RXD[ M1_RXD[ M1_RXD RE CLK K 5] 7] V M1_GTX_ CLK GND M1_TXER M1_RXD[ M1_RXD[ 2] 3] GND GND
VDD_IO
GND
GND
GND
GND
GND
GND
VDD_IO
RAM_AD RAM_AD RAM_AD RAM_AD RAM_AD DR[9] DR[10] DR[11] DR[13] DR[16] RAM_AD RAM_AD RAM_AD RAM_AD IC_GND DR[12] DR[14] DR[15] DR[19] RAM_AD RAM_AD RAM_BW IC_GND DR[17] DR[18] _B GND
VDD_IO
GND
GND
GND
GND
GND
GND
VDD_IO
M1_TXD[ M1_TXD[ M1_TXEN 2] 6]
M1_RXD[ M1_RXD[ 4] 6]
IC
VDD_IO
GND
GND
GND
GND
GND
GND
VDD_IO
M1_TXD[ M1_TXD[ M1_TXD[ M1_TXD[ M1_COL M1_RXD[ 0] 3] 5] 7] 1] VDD_CO M1_TXD[ M1_TXD[ RE 1] 4] GND M1_RBC1 M1_RXD[ 0]
A1VDD
VDD_IO
GND
GND
GND
GND
GND
GND
VDD_IO
PLL_PRI RAM_BW RAM_BW RAM_RW SYSTEM SYSTEM _A _C _DEBUG _CLK PLL_SEC RAM_BW RAM_BW SYSTEM GPIO[2] VDD_CO _D _F _RST RE RAM_BW RAM_BW GPIO[0] _E _G RAM_BW GPIO[4] _H GPIO[1] GPIO[7] GPIO[3] GPIO[9] RAM_DA TA[33]
VDD_IO
VDD_IO
M0_GTX_ M0_RXD[ M0_RXD[ M0_TXCL M0_CRS M1_RBC0 CLK 2] 5] K M0_TXD[ M0_TXERM0_TXEN M0_RXD[ M0_RXD M0_RXE 7] 4] V R M0_TXD[ M0_TXD[ M0_TXD[ M0_RXD[ M0_RXD[ M0_RXD[ 2] 5] 6] 6] 7] 3] VDD_CO M0_TXD[ M0_TXD[ M0_RBC0 M0_COL M0_RXD[ RE 1] 4] 1]
VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO
GPIO[6] GPIO[10] RAM_DA VDD_CO TA[32] RE GPIO[8] GPIO[15] RAM_DA TA[39] GND RAM_DA RAM_DA VDD_CO JTAG_TM CPU_AD CPU_AD VDD_CO VDD_CO CPU_DAT CPU_DAT CPU_DAT VDD_CO TA[45] TA[52] RE S DR[2] DR[12] RE RE A[8] A[15] A[23] RE GND N/C N/C
GND
M0_TXD[ M0_TXD[ M0_REF M0_RBC1 M0_RXD[ 0] 3] CLK 0] M0_RXCL K N/C N/C N/C M1_ACTI VE_LED N/C N/C
GPIO[5] GPIO[11] GPIO[14] RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA TEST_M TA[38] TA[43] TA[44] TA[51] TA[60] ODE[1]
CPU_AD CPU_AD CPU_AD CPU_TA CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT DR[6] DR[14] DR[23] A[1] A[7] A[12] A[22] A[30] IC
N/C
N/C
GPIO[12] GPIO[13] RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA TEST_M JTAG_TD CPU_AD CPU_AD CPU_AD CPU_AD CPU_CLK CPU_DR TA[37] TA[42] TA[46] TA[49] TA[59] ODE[0] O DR[4] DR[9] DR[16] DR[22] EQ0
CPU_DAT CPU_DAT CPU_DAT CPU_DAT A[10] A[16] A[21] A[27]
N/C
N/C
N/C
M0_ACTI VE_LED N/C
RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA JTAG_TC IC_GND CPU_AD CPU_AD CPU_AD CPU_AD CPU_WE CPU_SD CPU_IRE CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT TA[34] TA[36] TA[41] TA[47] TA[53] TA[58] TA[63] K DR[7] DR[11] DR[17] ACK2 Q1 A[3] A[6] A[14] A[20] A[24] A[29] DR[21] RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA JTAG_TR IC_GND CPU_AD CPU_AD CPU_AD CPU_AD CPU_AD CPU_OE CPU_TS_ CPU_DR TA[35] TA[40] TA[48] TA[54] TA[57] TA[62] ST DR[3] DR[8] DR[13] DR[18] DR[20] ALE EQ1 GND RAM_DA RAM_DA RAM_DA RAM_DA TEST_M JTAG_TDI IC_GND CPU_AD CPU_AD CPU_AD CPU_AD TA[50] TA[55] TA[56] TA[61] ODE[2] DR[5] DR[10] DR[15] DR[19] GND IC
N/C
N/C
N/C
CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT A[4] A[9] A[13] A[18] A[25] A[28]
N/C
N/C
N/C
CPU_CS CPU_SD IC_VDD_I CPU_IRE CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT ACK1 O Q0 A[0] A[5] A[2] A[11] A[17] A[19] A[26] A[31]
GND
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
12
3456
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Figure 3 - ZL50110 Package View and Ball Positions
14
Zarlink Semiconductor Inc.
ZL50110/11/14
ZL50114 Package view from TOP side. Note that ball A1 is non-chamfered corner
Data Sheet
12 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
GND
3456
N/C N/C N/C N/C N/C
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
N/C N/C N/C N/C N/C N/C GND N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C GND N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C
TDM_STo TDM_CL [1] Ko[3]
TDM_FR TDM_STo TDM_STi[ TDM_CL Mo_REF [0] 2] Ki[3]
TDM_CL TDM_FR TDM_CL TDM_CL TDM_STi[ TDM_CL KiP Mi_REF Ki_REF Ko[1] 3] Ko[2]
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
RAM_DA RAM_DA TDM_CL RAM_DA TDM_STi[ TDM_CL TDM_STo TA[3] TA[1] KiS TA[0] 0] Ki[1] [3] RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA TDM_CL TDM_CL TA[10] TA[9] TA[5] TA[4] TA[2] Ko_REF Ki[0] RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA TA[15] TA[13] TA[12] TA[6] TA[7] GND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
TDM_STi[ 1]
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
GND
N/C
N/C
N/C
N/C
VDD_CO TDM_STo TDM_CL TDM_CL RE [2] Ko[0] Ki[2]
N/C
VDD_CO RE
N/C
N/C
VDD_CO RE
N/C
N/C
N/C
N/C
VDD_CO RE
GND
N/C
N/C
N/C
N/C
N/C
RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA TA[21] TA[18] TA[16] TA[14] TA[11] TA[8] RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA VDD_CO TA[25] TA[24] TA[23] TA[19] TA[17] RE RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA TA[29] TA[28] TA[27] TA[26] TA[22] TA[20] RAM_PA RAM_PA RAM_DA RAM_DA RITY[1] RITY[0] TA[31] TA[30] GND VDD_CO RE VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO
N/C
N/C
M1_LINK M0_LINK M1_GIGA M_MDIO UP_LED UP_LED BIT_LED N/C N/C N/C
VDD_CO M0_GIGA M_MDC RE BIT_LED N/C N/C N/C
N/C
N/C
N/C
VDD_IO
VDD_IO
VDD_CO RE
GND
N/C
N/C
N/C
N/C
RAM_PA RAM_PA RAM_PA RAM_PA RAM_PA RAM_PA RITY[7] RITY[6] RITY[5] RITY[4] RITY[3] RITY[2] RAM_AD RAM_AD RAM_AD RAM_AD RAM_AD RAM_AD DR[5] DR[4] DR[2] DR[3] DR[0] DR[1] GND RAM_AD RAM_AD RAM_AD DR[6] DR[7] DR[8] GND VDD_CO RE GND
VDD_IO
GND
GND
GND
GND
GND
GND
VDD_IO
M1_RXE M1_TXCL M1_CRS R K
N/C
N/C
N/C
VDD_IO
GND
GND
GND
GND
GND
GND
VDD_IO
VDD_CO M1_REF M1_RXCL M1_RXD[ M1_RXD[ M1_RXD RE CLK K 5] 7] V M1_GTX_ CLK GND M1_TXER M1_RXD[ M1_RXD[ 2] 3] GND GND
VDD_IO
GND
GND
GND
GND
GND
GND
VDD_IO
RAM_AD RAM_AD RAM_AD RAM_AD RAM_AD DR[9] DR[10] DR[11] DR[13] DR[16] RAM_AD RAM_AD RAM_AD RAM_AD IC_GND DR[12] DR[14] DR[15] DR[19] RAM_AD RAM_AD RAM_BW IC_GND DR[17] DR[18] _B GND
VDD_IO
GND
GND
GND
GND
GND
GND
VDD_IO
M1_TXD[ M1_TXD[ M1_TXEN 2] 6]
M1_RXD[ M1_RXD[ 4] 6]
IC
VDD_IO
GND
GND
GND
GND
GND
GND
VDD_IO
M1_TXD[ M1_TXD[ M1_TXD[ M1_TXD[ M1_COL M1_RXD[ 0] 3] 5] 7] 1] VDD_CO M1_TXD[ M1_TXD[ RE 1] 4] GND M1_RBC1 M1_RXD[ 0]
A1VDD
VDD_IO
GND
GND
GND
GND
GND
GND
VDD_IO
PLL_PRI RAM_BW RAM_BW RAM_RW SYSTEM SYSTEM _A _C _DEBUG _CLK PLL_SEC RAM_BW RAM_BW SYSTEM GPIO[2] VDD_CO _D _F _RST RE RAM_BW RAM_BW GPIO[0] _E _G RAM_BW GPIO[4] _H GPIO[1] GPIO[7] GPIO[3] GPIO[9] RAM_DA TA[33]
VDD_IO
VDD_IO
M0_GTX_ M0_RXD[ M0_RXD[ M0_TXCL M0_CRS M1_RBC0 CLK 2] 5] K M0_TXD[ M0_TXERM0_TXEN M0_RXD[ M0_RXD M0_RXE 7] 4] V R M0_TXD[ M0_TXD[ M0_TXD[ M0_RXD[ M0_RXD[ M0_RXD[ 2] 5] 6] 6] 7] 3] VDD_CO M0_TXD[ M0_TXD[ M0_RBC0 M0_COL M0_RXD[ RE 1] 4] 1]
VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO
GPIO[6] GPIO[10] RAM_DA VDD_CO TA[32] RE GPIO[8] GPIO[15] RAM_DA TA[39] GND RAM_DA RAM_DA VDD_CO JTAG_TM CPU_AD CPU_AD VDD_CO VDD_CO CPU_DAT CPU_DAT CPU_DAT VDD_CO TA[45] TA[52] RE S DR[2] DR[12] RE RE A[8] A[15] A[23] RE GND N/C N/C
GND
M0_TXD[ M0_TXD[ M0_REF M0_RBC1 M0_RXD[ 0] 3] CLK 0] M0_RXCL K N/C N/C N/C M1_ACTI VE_LED N/C N/C
GPIO[5] GPIO[11] GPIO[14] RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA TEST_M TA[38] TA[43] TA[44] TA[51] TA[60] ODE[1]
CPU_AD CPU_AD CPU_AD CPU_TA CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT DR[6] DR[14] DR[23] A[1] A[7] A[12] A[22] A[30] IC
N/C
N/C
GPIO[12] GPIO[13] RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA TEST_M JTAG_TD CPU_AD CPU_AD CPU_AD CPU_AD CPU_CLK CPU_DR TA[37] TA[42] TA[46] TA[49] TA[59] ODE[0] O DR[4] DR[9] DR[16] DR[22] EQ0
CPU_DAT CPU_DAT CPU_DAT CPU_DAT A[10] A[16] A[21] A[27]
N/C
N/C
N/C
M0_ACTI VE_LED N/C
RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA JTAG_TC IC_GND CPU_AD CPU_AD CPU_AD CPU_AD CPU_WE CPU_SD CPU_IRE CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT TA[34] TA[36] TA[41] TA[47] TA[53] TA[58] TA[63] K DR[7] DR[11] DR[17] ACK2 Q1 A[3] A[6] A[14] A[20] A[24] A[29] DR[21] RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA JTAG_TR IC_GND CPU_AD CPU_AD CPU_AD CPU_AD CPU_AD CPU_OE CPU_TS_ CPU_DR TA[35] TA[40] TA[48] TA[54] TA[57] TA[62] ST DR[3] DR[8] DR[13] DR[18] DR[20] ALE EQ1 GND RAM_DA RAM_DA RAM_DA RAM_DA TEST_M JTAG_TDI IC_GND CPU_AD CPU_AD CPU_AD CPU_AD TA[50] TA[55] TA[56] TA[61] ODE[2] DR[5] DR[10] DR[15] DR[19] GND IC
N/C
N/C
N/C
CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT A[4] A[9] A[13] A[18] A[25] A[28]
N/C
N/C
N/C
CPU_CS CPU_SD IC_VDD_I CPU_IRE CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT ACK1 O Q0 A[0] A[5] A[2] A[11] A[17] A[19] A[26] A[31]
GND
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
12
3456
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Figure 4 - ZL50114 Package View and Ball Positions
15
Zarlink Semiconductor Inc.
ZL50110/11/14
Ball Signal Assignment Ball Number A1 A2 A3 A4 A5
Data Sheet
Ball Number D2 D3 D4 D5 D6 D7 D8 D9 D10 D11

Ball Number B14 B15 B16 B17 B18
Signal Name TDM_STi[13] TDM_CLKi[15] TDM_STi[15] TDM_STi[17] TDM_CLKi[18] TDM_CLKo[20] TDM_STo[19] TDM_STo[22] TDM_CLKo[23] TDM_STo[24] TDM_CLKo[26] TDM_STi[24] TDM_CLKo[27] TDM_CLKiP TDM_FRMi_REF TDM_CLKi_REF TDM_CLKo[1] TDM_STi[3] TDM_CLKo[2] TDM_CLKi[6] TDM_CLKi[7] TDM_CLKo[9] TDM_STo[9] TDM_STi[9] TDM_STi[11] TDM_CLKi[13] TDM_CLKo[14] TDM_CLKo[16] TDM_STi[16] TDM_CLKo[17] TDM_STi[19] TDM_CLKo[21] TDM_CLKi[21] TDM_CLKi[24] TDM_STi[22] TDM_STo[26] TDM_CLKi[27] TDM_STi[27] TDM_STi[28] RAM_DATA[3]
Signal Name RAM_DATA[1] TDM_CLKiS RAM_DATA[0] TDM_STi[0] TDM_CLKi[1] TDM_STo[3] TDM_STi[5] TDM_CLKi[5] TDM_CLKo[7] TDM_STi[8] TDM_CLKo[11] TDM_STi[12] TDM_STi[14] TDM_CLKi[16] TDM_CLKo[19] TDM_STo[18] TDM_STo[20] TDM_CLKo[22] TDM_STo[27] TDM_STo[25] TDM_CLKi[26] TDM_CLKo[28] TDM_CLKi[29] TDM_STi[29] TDM_STi[31] RAM_DATA[10] RAM_DATA[9] RAM_DATA[5] RAM_DATA[4] RAM_DATA[2] TDM_CLKo_REF TDM_CLKi[0] TDM_CLKo[4] TDM_STi[1] TDM_CLKi[4] TDM_STo[8] TDM_CLKi[8] TDM_CLKo[12] TDM_STo[15] TDM_CLKi[17]
Signal Name GND TDM_STo[1] TDM_CLKo[3] TDM_STo[4] TDM_STo[5] TDM_STi[6] TDM_STo[7] TDM_STi[7] TDM_CLKo[10] TDM_CLKi[10] TDM_CLKi[11] TDM_CLKo[13] GND TDM_STo[13] TDM_STo[14] TDM_CLKo[15] TDM_STo[16] TDM_CLKo[18] TDM_STi[18] TDM_CLKi[20] TDM_STi[20] TDM_STo[21] TDM_STi[21] TDM_CLKo[24] TDM_CLKo[25] GND TDM_FRMo_REF TDM_STo[0] TDM_STi[2] TDM_CLKi[3] TDM_STi[4] TDM_CLKo[6] TDM_STo[6] TDM_CLKo[8] TDM_CLKi[9] TDM_STo[10] TDM_STi[10] TDM_CLKi[12] TDM_STo[12]
B19 B20 B21 B22 B23 B25 C1 C2 C3 C4 C5 C6 C7 C8 C9

A6 A7 A8 A9 A10 A11

B24
D12 D13
A12 A13 A14 A15 A16 A18

B26
D14 D15 D16 D17

D18 D19 D20 D21 D22 D23 D25 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15

A17
A19 A20 A21 A22

C10 C11
D24
A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7

C12 C13 C14
D26
C15 C16 C17 C18 C19
C20 C21 C22 C23 C24 C25 C26 D1
B8 B9 B10 B11 B12
B13
16
Zarlink Semiconductor Inc.
ZL50110/11/14
Ball Number E16 E17 E18 E19

Data Sheet
Ball Number J24 J25 J26 K1 K2 K3 K4 K5 K6 K9 K18 K21 K22 K23 K24 K25 L1 L2 L3 L4 L5 L6 L9 L11 L12 L13 L14 L15 L16 L18 L21 L22 L23 L24 L25 L26 M1 M2 M3

Signal Name TDM_CLKi[19] TDM_STo[23] TDM_STi[23] TDM_CLKi[25] TDM_STi[26] TDM_CLKi[28] GND TDM_CLKo[30] TDM_CLKi[30] TDM_STi[30] TDM_STo[29] RAM_DATA[15] RAM_DATA[13] RAM_DATA[12] RAM_DATA[6] RAM_DATA[7] GND VDD_CORE TDM_STo[2] TDM_CLKo[0] TDM_CLKi[2] TDM_CLKo[5] VDD_CORE TDM_STo[11] TDM_CLKi[14] VDD_CORE TDM_STo[17] TDM_CLKi[22] TDM_STi[25] TDM_CLKi[23] VDD_CORE GND TDM_CLKi[31] TDM_CLKo[29] TDM_STo[28] TDM_CLKo[31] M1_LINKUP_LED RAM_DATA[21] RAM_DATA[18] RAM_DATA[16]
Ball Number G4 G5 G6 G21 G22

Signal Name RAM_DATA[14] RAM_DATA[11] RAM_DATA[8] TDM_STo[31] TDM_STo[30] M1/2_LINKUP_LED M0/3_LINKUP_LED M1_GIGABIT_LED M_MDIO RAM_DATA[25] RAM_DATA[24] RAM_DATA[23] RAM_DATA[19] RAM_DATA[17] VDD_CORE VDD_CORE M0_GIGABIT_LED M_MDC M3_CRS M3_TXCLK M3_RXER RAM_DATA[29] RAM_DATA[28] RAM_DATA[27] RAM_DATA[26] RAM_DATA[22] RAM_DATA[20] VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO M3_RXDV M3_RXD[3] M3_RXD[2]
Signal Name M3_RXD[1] M3_RXD[0] M3_COL RAM_PARITY[1] RAM_PARITY[0] RAM_DATA[31] RAM_DATA[30] GND VDD_CORE VDD_IO VDD_IO VDD_CORE GND M3_TXD[3] M3_TXEN M3_TXER M3_RXCLK RAM_PARITY[7] RAM_PARITY[6] RAM_PARITY[5] RAM_PARITY[4] RAM_PARITY[3] RAM_PARITY[2] VDD_IO GND GND GND GND GND GND VDD_IO M1_RXER M1_TXCLK M1_CRS M3_TXD[0] M3_TXD[1] M3_TXD[2] RAM_ADDR[5] RAM_ADDR[4] RAM_ADDR[2]
E20
E21 E22 E23 E24 E26 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11

G23 G24 G25 G26 H1 H2 H3 H4 H5 H6 H21 H22 H23 H24 H25 H26 J1 J2 J3 J4 J5 J6 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J21 J22 J23

E25
K26
F12 F13
F14 F15 F16
F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 G1 G2 G3
17
Zarlink Semiconductor Inc.
ZL50110/11/14
Ball Number M4 M5 M6 M9 M11 M12 M13 M14 M15 M16 M18 M21 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N6 N9 N11 N12 N13 N14 N15 N16 N18 N21 N22 N23 N24 N25 N26 P1 P2 P3 Signal Name RAM_ADDR[3] RAM_ADDR[0] RAM_ADDR[1] VDD_IO GND GND GND GND GND GND VDD_IO VDD_CORE M1_REFCLK M1_RXCLK M1_RXD[5] M1_RXD[7] M1_RXDV GND RAM_ADDR[6] RAM_ADDR[7] RAM_ADDR[8] GND VDD_CORE VDD_IO GND GND GND GND GND GND VDD_IO M1_GTX_CLK GND M1_TXER M1_RXD[2] M1_RXD[3] GND RAM_ADDR[9] RAM_ADDR[10] RAM_ADDR[11] Ball Number P4 P5 P6 P9 P11 P12 P13 P14 P15 P16 P18 P21 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R6 R9 R11 R12 R13 R14 R15 R16 R18 R21 R22 R23 R24 R25 R26 T1 T2 T3 Signal Name RAM_ADDR[13] RAM_ADDR[16] GND VDD_IO GND GND GND GND GND GND VDD_IO M1_TXD[2] M1_TXD[6] M1_TXEN GND M1_RXD[4] M1_RXD[6] RAM_ADDR[12] RAM_ADDR[14] RAM_ADDR[15] RAM_ADDR[19] IC_GND IC VDD_IO GND GND GND GND GND GND VDD_IO M1_TXD[0] M1_TXD[3] M1_TXD[5] M1_TXD[7] M1_COL M1_RXD[1] RAM_ADDR[17] RAM_ADDR[18] RAM_BW_B Ball Number T4 T5 T6 T9 T11 T12 T13 T14 T15 T16 T18 T21 T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U6 U9 U18 U21 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V6 V9 V10 V11
Data Sheet
Signal Name IC_GND GND A1VDD VDD_IO GND GND GND GND GND GND VDD_IO VDD_CORE M1_TXD[1] M1_TXD[4] GND M1_RBC1 M1_RXD[0] PLL_PRI RAM_BW_A RAM_BW_C RAM_RW SYSTEM_DEBUG SYSTEM_CLK VDD_IO VDD_IO M0_GTX_CLK M0_RXD[2] M0_RXD[5] M0_TXCLK M0_CRS M1_RBC0 PLL_SEC RAM_BW_D RAM_BW_F SYSTEM_RST GPIO[2] VDD_CORE VDD_IO VDD_IO VDD_IO
18
Zarlink Semiconductor Inc.
ZL50110/11/14
Ball Number V12 V13 V14 V15 V16 V17 V18 V21 V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W6 W21 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y6 Y21 Y22 Y23 Y24 Y25 Y26 AA1 AA2 AA3 Signal Name VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO M0_TXD[7] M0_TXER M0_TXEN M0_RXD[4] M0_RXDV M0_RXER RAM_BW_E RAM_BW_G GPIO[0] GPIO[3] GPIO[9] RAM_DATA[33] M0_TXD[2] M0_TXD[5] M0_TXD[6] M0_RXD[6] M0_RXD[7] M0_RXD[3] RAM_BW_H GPIO[4] GPIO[6] GPIO[10] RAM_DATA[32] VDD_CORE VDD_CORE M0_TXD[1] M0_TXD[4] M0_RBC0 M0_COL M0_RXD[1] GPIO[1] GPIO[7] GPIO[8] Ball Number AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19
Data Sheet
Ball Number AB18 AB19 AB20 AB21
Signal Name GPIO[15] RAM_DATA[39] GND RAM_DATA[45] RAM_DATA[52] VDD_CORE JTAG_TMS CPU_ADDR[2] CPU_ADDR[12] VDD_CORE VDD_CORE CPU_DATA[8] CPU_DATA[15] CPU_DATA[23] VDD_CORE M2_RXCLK M2_RXDV GND M0_TXD[0] M0_TXD[3] M0_REFCLK M0_RBC1 M0_RXD[0] GPIO[5] GPIO[11] GPIO[14] RAM_DATA[38] RAM_DATA[43] RAM_DATA[44] RAM_DATA[51] RAM_DATA[60] TEST_MODE[1] GND CPU_ADDR[6] CPU_ADDR[14] CPU_ADDR[23] CPU_TA CPU_DATA[1] CPU_DATA[7] CPU_DATA[12]
Signal Name CPU_DATA[22] CPU_DATA[30] M2_TXER M2_RXD[1] M0_RXCLK M0_LINKUP_LED M2_ACTIVE_LED M1_ACTIVE_LED M3_ACTIVE_LED GPIO[12] GPIO[13] RAM_DATA[37] RAM_DATA[42] RAM_DATA[46] RAM_DATA[49] RAM_DATA[59] TEST_MODE[0] JTAG_TDO CPU_ADDR[4] CPU_ADDR[9] CPU_ADDR[16] CPU_ADDR[22] CPU_CLK CPU_DREQ0 IC CPU_DATA[10] CPU_DATA[16] CPU_DATA[21] CPU_DATA[27] M2_TXD[1] M2_TXEN M2_RXD[2] M2_RXER M2_CRS M0_ACTIVE_LED RAM_DATA[34] RAM_DATA[36] RAM_DATA[41] RAM_DATA[47] RAM_DATA[53]
AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23
AA20 AA21 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17
AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5
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Zarlink Semiconductor Inc.
ZL50110/11/14
Ball Number AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19

Data Sheet
Signal Name RAM_DATA[58] RAM_DATA[63] JTAG_TCK IC_GND CPU_ADDR[7] CPU_ADDR[11] CPU_ADDR[17] CPU_ADDR[21] CPU_WE CPU_SDACK2 CPU_IREQ1 CPU_DATA[3] CPU_DATA[6] CPU_DATA[14] CPU_DATA[20] CPU_DATA[24] CPU_DATA[29] M2_TXD[2] M2_RXD[0] M2_RXD[3] M2_TXCLK RAM_DATA[35] RAM_DATA[40] RAM_DATA[48] RAM_DATA[54] RAM_DATA[57] RAM_DATA[62] JTAG_TRST IC_GND CPU_ADDR[3] CPU_ADDR[8] CPU_ADDR[13] CPU_ADDR[18] CPU_ADDR[20] CPU_OE CPU_TS_ALE CPU_DREQ1 IC CPU_DATA[4] CPU_DATA[9]
Ball Number AE20 AE21 AE22 AE23 AE24
Signal Name CPU_DATA[13] CPU_DATA[18] CPU_DATA[25] CPU_DATA[28] M2_TXD[0] M2_TXD[3] M2_COL GND RAM_DATA[50] RAM_DATA[55] RAM_DATA[56] RAM_DATA[61] TEST_MODE[2] JTAG_TDI IC_GND CPU_ADDR[5] CPU_ADDR[10] CPU_ADDR[15] CPU_ADDR[19] GND CPU_CS CPU_SDACK1 IC_VDD_IO CPU_IREQ0 CPU_DATA[0] CPU_DATA[5] CPU_DATA[2] CPU_DATA[11] CPU_DATA[17] CPU_DATA[19] CPU_DATA[26] CPU_DATA[31] GND
AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26
Not Connected on ZL50110 and ZL50114 leave open circuit. Not Connected on ZL50114 - leave open circuit. N/C - Not Connected - leave open circuit. IC - Internally Connected - leave open circuit. IC_GND - tie to ground IC_VDD_IO - tie to VDD_IO
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Zarlink Semiconductor Inc.
ZL50110/11/14
3.0 External Interface Description
Data Sheet
The following key applies to all tables: I O D U T Input Output Internal 100 k pull-down resistor present Internal 100 k pull-up resistor present Tri-state Output
3.1
TDM Interface
All TDM Interface signals are 5 V tolerant. All TDM Interface outputs are high impedance while System Reset is LOW. All TDM Interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be safely left unconnected if not used.
3.1.1
ZL50111 Variant TDM Stream Connection
Signal I/O ID [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] Package Balls D26 E25 D25 C26 C25 E20 F18 B25 E18 C22 A23 A21 C18 A19 B17 C16 [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] B16 D14 B14 D13 C12 B11 C11 D11 A8 A6 D8 B5 C5 B3 E9 D5 Description TDM port serial data input streams. For different standards these pins are given different identities: ST-BUS: TDM_STi[31:0] H.110: TDM_D[31:0] H-MVIP: TDM_HDS[31:0] Triggered on rising edge or falling edge depending on standard. At 8.192 Mbps only streams [7:0] are used, with 128 channels per stream. Streams [7:0] are used for J2, and streams [1:0] are used for T3, E3 pr STS-1.
TDM_STi[31:0]
Table 2 - TDM Interface ZL50111 Stream Pin Definition
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Zarlink Semiconductor Inc.
ZL50110/11/14
Signal TDM_STo[31:0] I/O OT [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] Package Balls G21 G22 E26 F24 D20 C23 D21 B23 E17 B21 A22 D18 B20 D17 F16 A17 F22 E24 D24 E21 C24 D22 E19 C21 F19 F17 C20 A20 E16 B18 E15 D15 [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] E14 A15 A14 B13 F13 B10 C10 E11 A7 B7 A5 A4 D7 F8 A2 B2 B15 F14 C13 B12 A11 A10 B9 E12 C8 C7 D9 E10 B4 F10 D6 E7 Description
Data Sheet
TDM port serial data output streams. For different standards these pins are given different identities: ST-BUS: TDM_STo[31:0] H.110: TDM_D[31:0] H-MVIP: TDM_HDS[31:0] Triggered on rising edge or falling edge depending on standard. At 8.192 Mbps only streams [7:0] are used, with 128 channels per stream. Streams [7:0] are used for J2, and streams [1:0] are used for T3, E3 or STS-1.
TDM_CLKi[31:0]
ID
TDM port clock inputs. Programmable as active high or low. Can accept frequencies of 1.544 MHz, 2.048 MHz, 4.096 MHz, 6.312 MHz, 8.192 MHz, 16.384 MHz, 34.368 MHz or 44.736 MHz depending on standard used. At 8.192 Mbps only streams [7:0] are used. Streams [7:0] are used for J2, and streams [1:0] are used for T3, E3 or STS-1.
Table 2 - TDM Interface ZL50111 Stream Pin Definition (continued)
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Zarlink Semiconductor Inc.
ZL50110/11/14
Signal TDM_CLKo[31:0] I/O O [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] Package Balls F25 E23 F23 D23 B26 B24 A25 A24 B22 D19 C19 B19 D16 A18 C17 C15 [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] A16 C14 A12 E13 D12 A9 C9 B8 D10 B6 F11 E8 A3 C6 C4 F9 Description
Data Sheet
TDM port clock outputs. Will generate 1.544 MHz, 2.048 MHz, 4.096 MHz, 6.312 MHz, 8.192 MHz, 16.384 MHz, 34.368 MHz or 44.736 MHz depending on standard used. At 8.192 Mbps only streams [7:0] are used. Streams [7:0] are used for J2, and streams [1:0] are used for T3, E3 or STS-1.
Table 2 - TDM Interface ZL50111 Stream Pin Definition (continued)
Note: Speed modes: 2.048 Mbps - all 32 streams active (bits [31:0]), with 32 channels per stream - 1024 total channels. 8.192 Mbps - 8 streams active (bits [7:0]), with 128 channels per stream - 1024 total channels. J2 - 8 streams active (bits [7:0]), with 98 channels per stream - 784 total channels. E3 - 2 streams active (bits [1:0]), with 537 channels per stream - 1074 total channels. T3 - 2 streams active (bits [1:0]), with 699 channels per stream - 1398 total channels. Note: All TDM Interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be safely left unconnected if not used.
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Zarlink Semiconductor Inc.
ZL50110/11/14
3.1.2 ZL50110 Variant TDM stream connection
Signal TDM_STi[7:0] I/O ID [7] [6] [5] [4] [3] [2] [1] [0] A8 A6 D8 B5 C5 B3 E9 D5 Package Balls Description
Data Sheet
TDM port serial data input streams. For different standards these pins are given different identities: ST-BUS: TDM_STi[7:0] H.110: TDM_D[7:0] H-MVIP: TDM_HDS[7:0] Triggered on rising edge or falling edge depending on standard. At 8.192 Mbps only streams [1:0] are used. Streams [1:0] are used for J2. TDM port serial data output streams. For different standards these pins are given different identities: ST-BUS: TDM_STo[7:0] H.110: TDM_D[7:0] H-MVIP: TDM_HDS[7:0] Triggered on rising edge or falling edge depending on standard. At 8.192 Mbps only streams [1:0] are used. Streams [1:0] are used for J2. TDM port clock inputs programmable as active high or low. Can accept frequencies of 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 6.312 MHz or 16.384 MHz depending on standard used. At 8.192 Mbps only streams [1:0] are used. Streams [1:0] are used for J2. TDM port clock outputs. Will generate 1.544 MHz, 2.048 MHz, 4.096 MHz, 6.312 MHz, 8.192 MHz or 16.384 MHz depending on standard used. At 8.192 Mbps only streams [1:0] are used. Streams [1:0] are used for J2.
TDM_STo[7:0]
OT
[7] [6] [5] [4] [3] [2] [1] [0]
A7 B7 A5 A4 D7 F8 A2 B2
TDM_CLKi[7:0]
ID
[7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0]
C8 C7 D9 E10 B4 F10 D6 E7 D10 B6 F11 E8 A3 C6 C4 F9
TDM_CLKo[7:0]
OT
Table 3 - TDM Interface ZL50110 Stream Pin Definition
Note: Speed modes: 2.048 Mbps - all 8 streams active (bits [7:0]), with 32 channels per stream - 256 total channels. 8.192 Mbps - 2 streams active (bits [1:0]), with 128 channels per stream - 256 total channels. J2 - 2 streams active (bits [1:0]), with 98 channels per stream - 196 total channels. Note: All TDM Interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be safely left unconnected if not used.
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Zarlink Semiconductor Inc.
ZL50110/11/14
3.1.3 ZL50114 Variant TDM Stream Connection
Signal TDM_STi[3:0] I/O ID [3] [2] [1] [0] C5 B3 E9 D5 Package Balls Description
Data Sheet
TDM port serial data input streams. For different standards these pins are given different identities: ST-BUS: TDM_STi[3:0] H.110: TDM_D[3:0] H-MVIP: TDM_HDS[3:0] Triggered on rising edge or falling edge depending on standard. At 8.192 Mbps only streams [1:0] are used. Streams [1:0] are used for J2. TDM port serial data output streams. For different standards these pins are given different identities: ST-BUS: TDM_STo[3:0] H.110: TDM_D[3:0] H-MVIP: TDM_HDS[3:0] Triggered on rising edge or falling edge depending on standard. At 8.192 Mbps only streams [1:0] are used. Streams [1:0] are used for J2. TDM port clock inputs programmable as active high or low. Can accept frequencies of 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 6.312 MHz or 16.384 MHz depending on standard used. At 8.192 Mbps only streams [1:0] are used. Streams [1:0] are used for J2. TDM port clock outputs. Will generate 1.544 MHz, 2.048 MHz, 4.096 MHz, 6.312 MHz, 8.192 MHz or 16.384 MHz depending on standard used. At 8.192 Mbps only streams [1:0] are used. Streams [1:0] are used for J2.
TDM_STo[3:0]
OT
[3] [2] [1] [0]
D7 F8 A2 B2
TDM_CLKi[3:0]
ID
[3] [2] [1] [0]
B4 F10 D6 E7
TDM_CLKo[3:0]
OT
[3] [2] [1] [0]
A3 C6 C4 F9
Table 4 - TDM Interface ZL50114 Stream Pin Definition
Note: Speed modes: 2.048 Mbps - all 4 streams active (bits [3:0]), with 32 channels per stream - 128 total channels. 8.192 Mbps - 2 streams active (bits [1:0]), with 128 channels per stream - 256 total channels. J2 - 2 streams active (bits [1:0]), with 98 channels per stream - 196 total channels. Note: All TDM Interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be safely left unconnected if not used.
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Zarlink Semiconductor Inc.
ZL50110/11/14
3.1.4 TDM Signals Common to ZL50111, ZL50110 and ZL50114
Signal TDM_CLKi_REF TDM_CLKo_REF TDM_FRMi_REF I/O ID O ID C3 E6 C2 Package Balls Description
Data Sheet
TDM port reference clock input for backplane operation TDM port reference clock output for backplane operation TDM port reference frame input. For different standards this pin is given a different identity: ST-BUS: TDM_F0i H.110: TDM_FRAME H-MVIP: TDM_F0 Signal is normally active low, but can be active high depending on standard. Indicates the start of a TDM frame by pulsing every 125 s. Normally will straddle rising edge or falling edge of clock pulse, depending on standard and clock frequency. TDM port reference frame output. For different standards this pin is given a different identity: ST-BUS: TDM_F0o H.110: TDM_FRAME H-MVIP: TDM_F0 Signal is normally active low, but can be active high depending on standard. Indicates the start of a TDM frame by pulsing every 125 s. Normally will straddle rising edge or falling edge of clock pulse, depending on standard and clock frequency.
TDM_FRMo_REF
O
B1
Table 5 - TDM Interface Common Pin Definition
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Zarlink Semiconductor Inc.
ZL50110/11/14
3.2 PAC Interface
Data Sheet
All PAC Interface signals are 5 V tolerant All PAC Interface outputs are high impedance while System Reset is LOW. Signal TDM_CLKiP I/O ID C1 Package Balls Description Primary reference clock input. Should be driven by external clock source to provide locking reference to internal / optional external DPLL in TDM master mode. Also provides PRS clock for RTP timestamps in synchronous modes. Acceptable frequency range: 8 kHz 34.368 MHz. Secondary reference clock input. Backup external reference for automatic switch-over in case of failure of TDM_CLKiP source. Primary reference output to optional external DPLL. Multiplexed & frequency divided reference output for support of optional external DPLL. Expected frequency range: 8 kHz - 16.384 MHz. Secondary reference output to optional external DPLL Multiplexed & frequency divided reference output for support of optional external DPLL. Expected frequency range: 8 kHz - 16.384 MHz.
TDM_CLKiS
ID
D3
PLL_PRI
OT
U1
PLL_SEC
OT
V1
Table 6 - PAC Interface Package Ball Definition
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Zarlink Semiconductor Inc.
ZL50110/11/14
3.3 Packet Interfaces
Data Sheet
For the ZL50111 variant the packet interface is capable of either 3 MII interfaces, 2 GMII interfaces or 2 TBI (1000 Mbps) interfaces. The TBI interface is a PCS interface supported by an integrated 1000BASE-X PCS module. The ZL50110 variant has either 2 MII interfaces, 2 GMII interfaces or 2 TBI (1000 Mbps) interfaces. Ports 2 and 3 are not available on the ZL50110 device. NOTE: In GMII/TBI mode only 1 GMAC port may be used to receive data. The second GMAC port is for redundancy purposes only. Data for all three types of packet switching is based on Specification IEEE Std. 802.3 - 2000. For the ZL50111 variant, only Ports 0 and 1 have the 1000 Mbps capability necessary for the GMII/TBI interface. In either GMII or TBI mode Ports 2 and 3 are disabled. Alternatively 3 ports can be used as 100 Mbps MII interfaces, either Ports 0, 1 and 2 or Ports 0, 1 and 3. Note: Port 2 and Port 3 can not be used to receive data simultaneously, they are mutually exclusive for packet reception. They may both be used for packet transmission if required. Table 7 maps the signal pins used in the MII interface to those used in the GMII and TBI interface. Table 8 shows all the pins and their related package ball, but is based on the GMII/MII configuration. All Packet Interface signals are 5V tolerant, and all outputs are high impedance while System Reset is LOW. MII Mn_LINKUP_LED Mn_ACTIVE_LED Mn_RXCLK Mn_COL Mn_RXD[3:0] Mn_RXDV Mn_RXER Mn_CRS Mn_TXCLK Mn_TXD[3:0] Mn_TXEN Mn_TXER GMII Mn_LINKUP_LED Mn_ACTIVE_LED Mn_GIGABIT_LED Mn_REFCLK Mn_RXCLK Mn_COL Mn_RXD[7:0] Mn_RXDV Mn_RXER Mn_CRS Mn_TXD[7:0] Mn_TXEN Mn_TXER Mn_GTX_CLK TBI (PCS) Mn_LINKUP_LED Mn_ACTIVE_LED Mn_GIGABIT_LED Mn_REFCLK Mn_RBC0 Mn_RBC1 Mn_RXD[7:0] Mn_RXD[8] Mn_RXD[9] Mn_Signal_Detect Mn_TXD[7:0] Mn_TXD[8] Mn_TXD[9] Mn_GTX_CLK
Table 7 - Packet Interface Signal Mapping - MII to GMII/TBI
Note: Mn can be either M0, M1, M2, or M3 for ZL50111 variant; and M0 or M1 for ZL50110 variant.
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Zarlink Semiconductor Inc.
ZL50110/11/14
Signal M_MDC I/O O H23 Package Balls Description
Data Sheet
MII management data clock. Common for all four MII ports. It has a minimum period of 400ns (maximum freq. 2.5 MHz), and is independent of the TXCLK and RXCLK. MII management data I/O. Common for all four MII ports at up to 2.5 MHz. It is bi-directional between the ZL50110/11/14 and the Ethernet station management entity. Data is passed synchronously with respect to M_MDC.
M_MDIO
ID/ OT
G26
Table 8 - MII Management Interface Package Ball Definition
MII Port 0 Signal M0_LINKUP_LED I/O O Package Balls G24 on ZL50110/4 AB23 on ZL50111 Description LED drive for MAC 0 to indicate port is linked up. Logic 0 output = LED on Logic 1 output = LED off LED drive for MAC 0 to indicate port is transmitting or receiving packet data. Logic 0 output = LED on Logic 1 output = LED off LED drive for MAC 0 to indicate operation at Gbps Logic 0 output = LED on Logic 1 output = LED off GMII/TBI - Reference Clock input at 125 MHz. Can be used to lock receive circuitry (RX) to M0_GTXCLK rather than recovering the RXCLK (or RBC0 and RBC1). Useful, for example, in the absence of valid serial data. NOTE: In MII mode this pin must be driven with the same clock as M0_RXCLK. GMII/MII - M0_RXCLK. Accepts the following frequencies: 25.0 MHz MII 100 Mbps 125.0 MHz GMII 1 Gbps
M0_ACTIVE_LED
O
AC26
M0_GIGABIT_LED
O
H22
M0_REFCLK
ID
AA24
M0_RXCLK
IU
AB22
Table 9 - MII Port 0 Interface Package Ball Definition
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Zarlink Semiconductor Inc.
ZL50110/11/14
MII Port 0 Signal M0_RBC0 I/O IU Y24 Package Balls Description
Data Sheet
TBI - M0_RBC0. Used as a clock when in TBI mode. Accepts 62.5 MHz, and is 180C out of phase with M0_RBC1. Receive data is clocked at each rising edge of M1_RBC1 and M1_RBC0, resulting in 125 MHz sample rate. TBI - M0_RBC1 Used as a clock when in TBI mode. Accepts 62.5 MHz, and is 180C out of phase with M0_RBC0. Receive data is clocked at each rising edge of M0_RBC1 and M0_RBC0, resulting in 125 MHz sample rate. GMII/MII - M0_COL. Collision Detection. This signal is independent of M0_TXCLK and M0_RXCLK, and is asserted when a collision is detected on an attempted transmission. It is active high, and only specified for half-duplex operation. W25 W24 U23 V24 [3] [2] [1] [0] W26 U22 Y26 AA26 Receive Data. Only half the bus (bits [3:0]) are used in MII mode. Clocked on rising edge of M0_RXCLK (GMII/MII) or the rising edges of M0_RBC0 and M0_RBC1 (TBI). GMII/MII - M0_RXDV Receive Data Valid. Active high. This signal is clocked on the rising edge of M0_RXCLK. It is asserted when valid data is on the M0_RXD bus. TBI - M0_RXD[8] Receive Data. Clocked on the rising edges of M0_RBC0 and M0_RBC1. GMII/MII - M0_RXER Receive Error. Active high signal indicating an error has been detected. Normally valid when M0_RXDV is asserted. Can be used in conjunction with M0_RXD when M0_RXDV signal is de-asserted to indicate a False Carrier. TBI - M0_RXD[9] Receive Data. Clocked on the rising edges of M0_RBC0 and M0_RBC1.
M0_RBC1
IU
AA25
M0_COL
ID
Y25
M0_RXD[7:0]
IU
[7] [6] [5] [4] V25
M0_RXDV / M0_RXD[8]
ID
M0_RXER / M0_RXD[9]
ID
V26
Table 9 - MII Port 0 Interface Package Ball Definition (continued)
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Zarlink Semiconductor Inc.
ZL50110/11/14
MII Port 0 Signal M0_CRS / M0_Signal_Detect I/O ID U25 Package Balls Description
Data Sheet
GMII/MII - M0_CRS Carrier Sense. This asynchronous signal is asserted when either the transmission or reception device is non-idle. It is active high. TBI - M0_Signal Detect Similar function to M0_CRS. MII only - Transmit Clock Accepts the following frequencies: 25.0 MHz MII 100 Mbps V21 W23 W22 Y23 [3] [2] [1] [0] AA23 W21 Y22 AA22 Transmit Data. Only half the bus (bits [3:0]) are used in MII mode. Clocked on rising edge of M0_TXCLK (MII) or the rising edge of M0_GTXCLK (GMII/TBI). GMII/MII - M0_TXEN Transmit Enable. Asserted when the MAC has data to transmit, synchronously to M0_TXCLK with the first pre-amble of the packet to be sent. Remains asserted until the end of the packet transmission. Active high. TBI - M0_TXD[8] Transmit Data. Clocked on rising edge of M0_GTXCLK. GMII/MII - M0_TXER Transmit Error. Transmitted synchronously with respect to M0_TXCLK, and active high. When asserted (with M0_TXEN also asserted) the ZL50110/11/14 will transmit a non-valid symbol, somewhere in the transmitted frame. TBI - M0_TXD[9] Transmit Data. Clocked on rising edge of M0_GTXCLK. GMII/TBI only - Gigabit Transmit Clock Output of a clock for Gigabit operation at 125 MHz.
M0_TXCLK
IU
U24
M0_TXD[7:0]
O
[7] [6] [5] [4] V23
M0_TXEN / M0_TXD[8]
O
M0_TXER / M0_TXD[9]
O
V22
M0_GTX_CLK
O
U21
Table 9 - MII Port 0 Interface Package Ball Definition (continued)
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Zarlink Semiconductor Inc.
ZL50110/11/14
MII Port 1 Signal M1_LINKUP_LED I/O O Package Balls G23 on ZL50110/4 F26 on ZL50111 Description
Data Sheet
LED drive for MAC 1 to indicate port is linked up. Logic 0 output = LED on Logic 1 output = LED off LED drive for MAC 1 to indicate port is transmitting or receiving packet data. Logic 0 output = LED on Logic 1 output = LED off LED drive for MAC 1 to indicate operation at Gbps. Logic 0 output = LED on Logic 1 output = LED off GMII/TBI - Reference Clock input at 125 MHz. Can be used to lock receive circuitry (RX) to M1_GTXCLK rather than recovering the RXCLK (or RBC0 and RBC1). Useful, for example, in the absence of valid serial data. NOTE: In MII mode this pin must be driven with the same clock as M1_RXCLK. GMII/MII - M1_RXCLK. Accepts the following frequencies: 25.0 MHz MII 100 Mbps 125.0 MHz GMII 1 Gbps TBI - M1_RBC0. Used as a clock when in TBI mode. Accepts 62.5 MHz and is 180C out of phase with M1_RBC1. Receive data is clocked at each rising edge of M1_RBC1 and M1_RBC0, resulting in 125 MHz sample rate. TBI - M1_RBC1 Used as a clock when in TBI mode. Accepts 62.5 MHz, and is 180 out of phase with M1_RBC0. Receive data is clocked at each rising edge of M1_RBC1 and M1_RBC0, resulting in 125 MHz sample rate. GMII/MII - M1_COL. Collision Detection. This signal is independent of M1_TXCLK and M1_RXCLK, and is asserted when a collision is detected on an attempted transmission. It is active high, and only specified for half-duplex operation.
M1_ACTIVE_LED
O
AB25
M1_GIGABIT_LED
O
G25
M1_REFCLK
ID
M22
M1_RXCLK
IU
M23
M1_RBC0
IU
U26
M1_RBC1
IU
T25
M1_COL
ID
R25
Table 10 - MII Port 1 Interface Package Ball Definition
32
Zarlink Semiconductor Inc.
ZL50110/11/14
MII Port 1 Signal M1_RXD[7:0] I/O IU [7] [6] [5] [4] M26 Package Balls M25 P26 M24 P25 [3] [2] [1] [0] N25 N24 R26 T26 Description
Data Sheet
Receive Data. Only half the bus (bits [3:0]) are used in MII mode. Clocked on rising edge of M1_RXCLK (GMII/MII) or the rising edges of M1_RBC0 and M1_RBC1 (TBI). GMII/MII - M1_RXDV Receive Data Valid. Active high. This signal is clocked on the rising edge of M1_RXCLK. It is asserted when valid data is on the M1_RXD bus. TBI - M1_RXD[8] Receive Data. Clocked on the rising edges of M1_RBC0 and M1_RBC1. GMII/MII - M1_RXER Receive Error. Active high signal indicating an error has been detected. Normally valid when M1_RXDV is asserted. Can be used in conjunction with M1_RXD when M1_RXDV signal is de-asserted to indicate a False Carrier. TBI - M1_RXD[9] Receive Data. Clocked on the rising edges of M1_RBC0 and M1_RBC1. GMII/MII - M1_CRS Carrier Sense. This asynchronous signal is asserted when either the transmission or reception device is non-idle. It is active high. TBI - M1_Signal Detect Similar function to M1_CRS. MII only - Transmit Clock Accepts the following frequencies: 25.0 MHz MII 100 Mbps
M1_RXDV / M1_RXD[8]
ID
M1_RXER / M1_RXD[9]
ID
L21
M1_CRS / M1_Signal_Detect
ID
L23
M1_TXCLK
IU
L22
M1_TXD[7:0]
O
[7] [6] [5] [4] P23
R24 P22 R23 T23
[3] [2] [1] [0]
R22 P21 T22 R21
Transmit Data. Only half the bus (bits [3:0]) are used in MII mode. Clocked on rising edge of M1_TXCLK (MII) or the rising edge of M1_GTXCLK (GMII/TBI). GMII/MII - M1_TXEN Transmit Enable. Asserted when the MAC has data to transmit, synchronously to M1_TXCLK with the first pre-amble of the packet to be sent. Remains asserted until the end of the packet transmission. Active high. TBI - M1_TXD[8] Transmit Data. Clocked on rising edge of M1_GTXCLK.
M1_TXEN / M1_TXD[8]
O
Table 10 - MII Port 1 Interface Package Ball Definition (continued)
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Zarlink Semiconductor Inc.
ZL50110/11/14
MII Port 1 Signal M1_TXER / M1_TXD[9] I/O O N23 Package Balls Description
Data Sheet
GMII/MII - M1_TXER Transmit Error. Transmitted synchronously with respect to M1_TXCLK, and active high. When asserted (with M1_TXEN also asserted) the ZL50110/11/14 will transmit a non-valid symbol, somewhere in the transmitted frame. TBI - M1_TXD[9] Transmit Data. Clocked on rising edge of M1_GTXCLK. GMII/TBI only - Gigabit Transmit Clock Output of a clock for Gigabit operation at 125 MHz.
M1_GTX_CLK
O
N21
Table 10 - MII Port 1 Interface Package Ball Definition (continued)
MII Port 2 - ZL50111 variant only. Note: This port must not be used to receive data at the same time as port 3, they are mutually exclusive. Signal M2_LINKUP_LED I/O O G23 Package Balls Description LED drive for MAC 2 to indicate port is linked up. Logic 0 output = LED on Logic 1 output = LED off LED drive for MAC 2 to indicate port is transmitting or receiving packet data. Logic 0 output = LED on Logic 1 output = LED off MII only - Receive Clock. Accepts the following frequencies: 25.0 MHz MII 100 Mbps Collision Detection. This signal is independent of M2_TXCLK and M2_RXCLK, and is asserted when a collision is detected on an attempted transmission. It is active high, and only specified for half-duplex operation. AD25 AC23 [1] [0] AB21 AD24 Receive Data. Clocked on rising edge of M2_RXCLK. Receive Data Valid. Active high. This signal is clocked on the rising edge of M2_RXCLK. It is asserted when valid data is on the M2_RXD bus.
M2_ACTIVE_LED
O
AB24
M2_RXCLK
IU
AA19
M2_COL
ID
AE26
M2_RXD[3:0] M2_RXDV
IU ID
[3] [2] AA20
Table 11 - MII Port 2 Interface Package Ball Definition
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Zarlink Semiconductor Inc.
ZL50110/11/14
MII Port 2 - ZL50111 variant only. Note: This port must not be used to receive data at the same time as port 3, they are mutually exclusive. Signal M2_RXER I/O ID AC24 Package Balls Description
Data Sheet
Receive Error. Active high signal indicating an error has been detected. Normally valid when M2_RXDV is asserted. Can be used in conjunction with M2_RXD when M2_RXDV signal is de-asserted to indicate a False Carrier. Carrier Sense. This asynchronous signal is asserted when either the transmission or reception device is non-idle. It is active high. MII only - Transmit Clock Accepts the following frequencies: 25.0 MHz MII 100 Mbps AE25 AD23 [1] [0] AC21 AE24 Transmit Data. Clocked on rising edge of M2_TXCLK. Transmit Enable. Asserted when the MAC has data to transmit, synchronously to M2_TXCLK with the first pre-amble of the packet to be sent. Remains asserted until the end of the packet transmission. Active high. Transmit Error. Transmitted synchronously with respect to M2_TXCLK, and active high. When asserted (with M2_TXEN also asserted) the ZL50110/11/14 will transmit a non-valid symbol, somewhere in the transmitted frame.
M2_CRS
ID
AC25
M2_TXCLK
IU
AD26
M2_TXD[3:0] M2_TXEN
O O
[3] [2] AC22
M2_TXER
O
AB20
Table 11 - MII Port 2 Interface Package Ball Definition (continued)
MII Port 3 - ZL50111 variant only Note: This port must not be used to receive data at the same time as port 2, they are mutually exclusive. Signal M3_LINKUP_LED I/O O G24 Package Balls Description LED drive for MAC 3 to indicate port is linked up. Logic 0 output = LED on Logic 1 output = LED off LED drive for MAC 3 to indicate port is transmitting or receiving packet data. Logic 0 output = LED on Logic 1 output = LED off
M3_ACTIVE_LED
O
AB26
Table 12 - MII Port 3 Interface Package Ball Definition
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Zarlink Semiconductor Inc.
ZL50110/11/14
MII Port 3 - ZL50111 variant only Note: This port must not be used to receive data at the same time as port 2, they are mutually exclusive. Signal M3_RXCLK I/O IU K26 Package Balls Description
Data Sheet
MII only - Receive Clock. Accepts the following frequencies: 25.0 MHz MII 100 Mbps Collision Detection. This signal is independent of M3_TXCLK and M3_RXCLK, and is asserted when a collision is detected on an attempted transmission. It is active high, and only specified for half-duplex operation. J22 J23 [1] [0] J24 J25 Receive Data. Clocked on rising edge of M3_RXCLK. Receive Data Valid. Active high. This signal is clocked on the rising edge of M3_RXCLK. It is asserted when valid data is on the M3_RXD bus. Receive Error. Active high signal indicating an error has been detected. Normally valid when M3_RXDV is asserted. Can be used in conjunction with M3_RXD when M3_RXDV signal is de-asserted to indicate a False Carrier. Carrier Sense. This asynchronous signal is asserted when either the transmission or reception device is non-idle. It is active high. MII only - Transmit Clock Accepts the following frequencies: 25.0 MHz MII 100 Mbps K23 L26 [1] [0] L25 L24 Transmit Data. Clocked on rising edge of M3_TXCLK. Transmit Enable. Asserted when the MAC has data to transmit, synchronously to M3_TXCLK with the first pre-amble of the packet to be sent. Remains asserted until the end of the packet transmission. Active high. Transmit Error. Transmitted synchronously with respect to M3_TXCLK, and active high. When asserted (with M3_TXEN also asserted) the ZL50110/11/14 will transmit a non-valid symbol, somewhere in the transmitted frame.
M3_COL
ID
J26
M3_RXD[3:0] M3_RXDV
IU ID
[3] [2] J21
M3_RXER
ID
H26
M3_CRS
ID
H24
M3_TXCLK
IU
H25
M3_TXD[3:0] M3_TXEN
O O
[3] [2] K24
M3_TXER
O
K25
Table 12 - MII Port 3 Interface Package Ball Definition (continued)
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Zarlink Semiconductor Inc.
ZL50110/11/14
3.4 External Memory Interface
Data Sheet
All External Memory Interface signals are 5 V tolerant. All External Memory Interface outputs are high impedance while System Reset is LOW. If the External Memory Interface is unused, all input pins may be left unconnected. Active low signals are designated by a # suffix, in accordance with the convention used in common memory data sheets. Signal RAM_DATA[63:0] I/O IU/ OT [63] [62] [61] [60] [59] [58] [57] [56] [55] [54] [53] [52] [51] [50] [49] [48] [47] [46] [45] [44] [43] [42] [41] [40] [39] [38] [37] [36] [35 [34] [33] [32] [7] [6] [5] [4] Package Balls AD7 AE6 AF5 AB8 AC7 AD6 AE5 AF4 AF3 AE4 AD5 AA8 AB7 AF2 AC6 AE3 AD4 AC5 AA7 AB6 AB5 AC4 AD3 AE2 AA5 AB4 AC3 AD2 AE1 AD1 W6 Y5 L1 L2 L3 L4 [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] [3] [2] [1] [0] K3 K4 J1 J2 J3 J4 H1 H2 H3 J5 G1 J6 H4 G2 H5 G3 F1 G4 F2 F3 G5 E1 E2 G6 F5 F4 E3 E4 D1 E5 D2 D4 L5 L6 K1 K2 Description Buffer memory data. Synchronous to rising edge of SYSTEM_CLK.
RAM_PARITY[7:0]
IU/ OT
Buffer memory parity. Synchronous to rising edge of SYSTEM_CLK. Bit [7] is parity for data byte [63:56], bit [0] is parity for data byte [7:0].
Table 13 - External Memory Interface Package Ball Definition
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Zarlink Semiconductor Inc.
ZL50110/11/14
Signal RAM_ADDR[19:0] I/O O [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] U2 R4 T2 T1 P5 R3 R2 P4 R1 P3 P2 Package Balls [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] P1 N4 N3 N2 M1 M2 M4 M3 M6 M5 Description Buffer memory address output. Synchronous to rising edge of SYSTEM_CLK.
Data Sheet
RAM_BW_A#
O
Synchronous Byte Write Enable A (Active Low). Must be asserted same clock cycle as RAM_ADDR. Enables RAM_DATA[7:0]. Synchronous Byte Write Enable B (Active Low). Must be asserted same clock cycle as RAM_ADDR. Enables RAM_DATA[15:8]. Synchronous Byte Write Enable C (Active Low). Must be asserted same clock cycle as RAM_ADDR. Enables RAM_DATA[23:16]. Synchronous Byte Write Enable D (Active Low). Must be asserted same clock cycle as RAM_ADDR. Enables RAM_DATA[31:24]. Synchronous Byte Write Enable E (Active Low). Must be asserted same clock cycle as RAM_ADDR. Enables RAM_DATA[39:32]. Synchronous Byte Write Enable F (Active Low). Must be asserted same clock cycle as RAM_ADDR. Enables RAM_DATA[47:40]. Synchronous Byte Write Enable G (Active Low). Must be asserted same clock cycle as RAM_ADDR. Enables RAM_DATA[55:48]. Synchronous Byte Write Enable H (Active Low). Must be asserted same clock cycle as RAM_ADDR. Enables RAM_DATA[63:56]. Read/Write Enable output Read = high Write = low
RAM_BW_B#
O
T3
RAM_BW_C#
O
U3
RAM_BW_D#
O
V2
RAM_BW_E#
O
W1
RAM_BW_F#
O
V3
RAM_BW_G#
O
W2
RAM_BW_H#
O
Y1
RAM_RW#
O
U4
Table 13 - External Memory Interface Package Ball Definition (continued)
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Zarlink Semiconductor Inc.
ZL50110/11/14
3.5 CPU Interface
Data Sheet
All CPU Interface signals are 5 V tolerant. All CPU Interface outputs are high impedance while System Reset is LOW. Signal CPU_DATA[31:0] I/O I/ OT [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] AF14 Package Balls AF25 AB19 AD22 AE23 AC20 AF24 AE22 AD21 AA17 AB18 AC19 AD20 AF23 AE21 AF22 AC18 AB13 AC13 AD13 AE13 AF12 AE12 AD12 AC12 AF11 AB12 AE11 AA12 [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] AA16 AD19 AE20 AB17 AF21 AC17 AE19 AA15 AB16 AD18 AF19 AE18 AD17 AF20 AB15 AF18 AD11 AF10 AC11 AE10 AD10 AB11 AF9 AC10 AE9 AA11 Description CPU Data Bus. Bi-directional data bus, synchronously transmitted with CPU_CLK rising edge. NOTE: as with all ports in the ZL50110/11/14 device, CPU_DATA[0] is the least significant bit (lsb).
CPU_ADDR[23:2]
I
CPU Address Bus. Address input from processor to ZL50110/11/14, synchronously transmitted with CPU_CLK rising edge. NOTE: as with all ports in the ZL50110/11/14 device, CPU_ADDR[2] is the least significant bit (lsb).
CPU_CS
IU
CPU Chip Select. Synchronous to rising edge of CPU_CLK and active low. Is asserted with CPU_TS_ALE. Must be asserted with CPU_OE to asynchronously enable the CPU_DATA output during a read, including DMA read. CPU Write Enable. Synchronously asserted with respect to CPU_CLK rising edge, and active low. Used for CPU writes from the processor to registers within the ZL50110/11/14. Asserted one clock cycle after CPU_TS_ALE.
CPU_WE
I
AD14
Table 14 - CPU Interface Package Ball Definition
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Zarlink Semiconductor Inc.
ZL50110/11/14
Signal CPU_OE I/O I AE14 Package Balls Description
Data Sheet
CPU Output Enable. Synchronously asserted with respect to CPU_CLK rising edge, and active low. Used for CPU reads from the processor to registers within the ZL50110/11/14. Asserted one clock cycle after CPU_TS_ALE. Must be asserted with CPU_CS to asynchronously enable the CPU_DATA output during a read, including DMA read. Synchronous input with rising edge of CPU_CLK. Latch Enable (ALE), active high signal. Asserted with CPU_CS, for a single clock cycle. CPU/DMA 1 Acknowledge Input. Active low synchronous to CPU_CLK rising edge. Used to acknowledge request from ZL50110/11/14 for a DMA write transaction. Only used for DMA transfers, not for normal register access. CPU/DMA 2 Acknowledge Input Active low synchronous to CPU_CLK rising edge. Used to acknowledge request from ZL50110/11/14 for a DMA read transaction. Only used for DMA transfers, not for normal register access. CPU PowerQUICCTM II Bus Interface clock input. 66 MHz clock, with minimum of 6 ns high/low time. Used to time all host interface signals into and out of ZL50110/11/14 device. CPU Transfer Acknowledge. Driven from tri-state condition on the negative clock edge of CPU_CLK following the assertion of CPU_CS. Active low, asserted from the rising edge of CPU_CLK. For a read, asserted when valid data is available at CPU_DATA. The data is then read by the host on the following rising edge of CPU_CLK. For a write, is asserted when the ZL50110/11/14 is ready to accept data from the host. The data is written on the rising edge of CPU_CLK following the assertion. Returns to tri-state from the negative clock edge of CPU_CLK following the de-assertion of CPU_CS.
CPU_TS_ALE
I
AE15
CPU_SDACK1
I
AF15
CPU_SDACK2
I
AD15
CPU_CLK
I
AC14
CPU_TA
OT
AB14
Table 14 - CPU Interface Package Ball Definition (continued)
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Zarlink Semiconductor Inc.
ZL50110/11/14
Signal CPU_DREQ0 I/O OT AC15 Package Balls Description
Data Sheet
CPU DMA 0 Request Output Active low synchronous to CPU_CLK rising edge. Asserted by ZL50110/11/14 to request the host initiates a DMA write. Only used for DMA transfers, not for normal register access. CPU DMA 1 Request Active low synchronous to CPU_CLK rising edge. Asserted by ZL50110/11/14 to indicate packet data is ready for transmission to the CPU, and request the host initiates a DMA read. Only used for DMA transfers, not for normal register access. CPU Interrupt 0 Request (Active Low) CPU Interrupt 1 Request (Active Low)
CPU_DREQ1
OT
AE16
CPU_IREQO CPU_IREQ1
O O
AF17 AD16
Table 14 - CPU Interface Package Ball Definition (continued)
3.6
System Function Interface
All System Function Interface signals are 5 V tolerant. The core of the chip will be held in reset for 16383 SYSTEM_CLK cycles after SYSTEM_RST has gone HIGH to allow the PLL's to lock. Signal SYSTEM_CLK I/O I U6 Package Balls Description System Clock Input. The system clock frequency is 100 MHz. The frequency must be accurate to within 32 ppm in synchronous mode. The quality of SYSTEM_CLK, or the oscillator that drives SYSTEM_CLK directly impacts the adaptive clock recovery performance. See Section 6.3. System Reset Input. Active low. The system reset is asynchronous, and causes all registers within the ZL50110/11/14 to be reset to their default state. Recommend external pull-up. System Debug Enable. This is an asynchronous signal that, when de-asserted, prevents the software assertion of the debug-freeze command, regardless of the internal state of registers, or any error conditions. Active high. Recommend external pull-down.
SYSTEM_RST
I
V4
SYSTEM_DEBUG
I
U5
Table 15 - System Function Interface Package Ball Definition
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Zarlink Semiconductor Inc.
ZL50110/11/14
3.7 3.7.1 Test Facilities Administration, Control and Test Interface
Data Sheet
All Administration, Control and Test Interface signals are 5 V tolerant. Signal GPIO[15:0] I/O ID/ OT [15] [14] [13] [12] [11] [10] [9] [8] [2] [1] [0] Package Balls AA4 AB3 AC2 AC1 AB2 Y4 W5 AA3 AF6 AB9 AC8 [7] [6] [5] [4] [3] [2] [1] [0] AA2 Y3 AB1 Y2 W4 V5 AA1 W3 Description General Purpose I/O pins. Connected to an internal register, so customer can set user-defined parameters. Bits [4:0] reserved at startup or reset for memory TDL setup. See the ZL50110/11/14 Programmers Model for more details. Recommend 5 kohm pulldown on these signals. Test Mode input - ensure these pins are tied to ground for normal operation. 000 SYS_NORMAL_MODE 001-010 RESERVED 011 SYS_TRISTATE_MODE 100-111 RESERVED
TEST_MODE[2:0]
ID
Table 16 - Administration/Control Interface Package Ball Definition
3.7.2
JTAG Interface
All JTAG Interface signals are 5 V tolerant, and conform to the requirements of IEEE1149.1 (2001). Signal JTAG_TRST I/O IU AE7 Package Balls Description JTAG Reset. Asynchronous reset. In normal operation this pin should be pulled low. Recommend external pull-down. JTAG Clock - maximum frequency is 25MHz, typically run at 10 MHz. In normal operation this pin should be pulled either high or low. Recommend external pull-down. JTAG test mode select. Synchronous to JTAG_TCK rising edge. Used by the Test Access Port controller to set certain test modes. JTAG test data input. Synchronous to JTAG_TCK. JTAG test data output. Synchronous to JTAG_TCK.
JTAG_TCK
I
AD8
JTAG_TMS
IU
AA10
JTAG_TDI JTAG_TDO
IU O
AF7 AC9
Table 17 - JTAG Interface Package Ball Definition
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Zarlink Semiconductor Inc.
ZL50110/11/14
3.8 Miscellaneous Inputs
Signal IC_GND IC_VDD_IO AF16 Package Balls AD9, AF8, R5, T4, AE8 Description Internally Connected. Tie to GND.
Data Sheet
Internally Connected. Tie to VDD_IO.
Table 18 - Miscellaneous Inputs Package Ball Definitions
3.9
Power and Ground Connections
Signal Package Balls J9 J13 J17 L9 N9 R9 U9 V11 V15 A1 F6 L11 L15 M13 N1 N13 N22 P12 P16 R13 T5 T14 AA6 AF13 F7 F20 K6 N6 Y6 AA13 T6 J10 J14 J18 L18 N18 R18 U18 V12 V16 A13 F21 L12 L16 M14 N5 N14 N26 P13 P24 R14 T11 T15 AA21 AF26 F12 H6 K21 T21 Y21 AA14 J11 J15 K9 M9 P9 T9 V9 V13 V17 A26 K5 L13 M11 M15 N11 N15 P6 P14 R11 R15 T12 T16 AB10 F15 H21 M21 V6 AA9 AA18 J12 J16 K18 M18 P18 T18 V10 V14 V18 E22 K22 L14 M12 M16 N12 N16 P11 P15 R12 R16 T13 T24 AF1 Description 3.3 V VDD Power Supply for IO Ring
VDD_IO
GND
0 V Ground Supply
VDD_CORE
1.8 V VDD Power Supply for Core Region
A1VDD
1.8 V PLL Power Supply Table 19 - Power and Ground Package Ball Definition
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Zarlink Semiconductor Inc.
ZL50110/11/14
3.10 Internal Connections
Signal IC Package Balls R6, AC16, AE17 Description
Data Sheet
Internally Connected. Must leave open circuit.
Table 20 - No Connection Ball Definition
4.0
4.1
Typical Applications
Leased Line Provision
Circuit emulation is typically used to support the provision of leased line services to customers using legacy TDM equipment. For example, Figure 5 shows a leased line TDM service being carried across a packet network. The advantages are that a carrier can upgrade to a packet switched network, whilst still maintaining their existing TDM business. The ZL50110/11/14 is capable of handling circuit emulation of both structured T1, E1, and J2 links (e.g., for support of fractional circuits) and unstructured (or clear channel) T1, E1, J2, T3, E3 and STS-1 links. The device handles the data-plane requirements of the provider edge inter-working function (with the exception of the physical interfaces and line interface units). Control plane functions are forwarded to the host processor controlling the ZL50110/11/14 device. The ZL50110/11/14 provides a per-stream clock recovery function to reproduce the TDM service frequency at the egress of the packet network. This is required otherwise the queue at the egress of the packet network will either fill up or empty, depending on whether the regenerated clock is slower or faster than the original.
Customer Premises
Customer data
Carrier Network
Customer Premises
queue Customer data
TDM
TDM to packet
Packet Network
TDM
fservice
~
fservice
Provider Edge Interworking Function
~
fservice
Provider Edge Interworking Function
Extract Clock
Figure 5 - Leased Line Services Over a Circuit Emulation Link
4.2
Metropolitan Area Network Aggregation
The metro Ethernet application, shown in Figure 6, consists of the metro Ethernet service modules sitting on the edge of the Metro Ethernet ring. The modules will connect Ethernet circuits and TDM circuits to the metro ring. The ZL50110/11/14 is used to emulate leased line TDM circuits over Ethernet by establishing CESoP connections over the Metro Ethernet ring between the MTUs/MDUs and the PSTN. The use of CESoP eliminates the need for a separate TDM network in the metro core, thereby enabled convergence on a unified Ethernet network.
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Zarlink Semiconductor Inc.
ZL50110/11/14
Data Sheet
OC-3, DS3
CESoP
Multi-Tenant Units
Metro Core
CESoP
Campus
Metropolitan Access Network
(Resilient Packet Ring or Metro Ethernet)
Metro Access
T1/E1 Links
Metro Access
T1/E1 Links
Figure 6 - Metropolitan Area Network Aggregation using CESoP
4.3
Digital Loop Carrier
The Broadband Digital Loop Carrier (BBDLC) application, shown in Figure 7, consists of a BBDLC connected to the Central Office (CO) by a dedicated fiber link running Gigabit Ethernet (GE) rather than by NxT1/E1 or DS3/E3. The ZL50110/11/14 is used to emulate TDM circuits over Ethernet by establishing CESoP connections between the BBDLC and the CO. At the CO the native IP or Ethernet traffic is split from the CESoP connections at sent towards the packet network. Multiple T1/E1 CESoP connections from several BBDLC are aggregated in the CO using a larger ZL50110/11/14 variant, converted back to TDM circuits, and connected to a class 5 switch destined towards the PSTN. In this configuration T3/E3 services can also be provided. Using CESoP allows voice and data traffic to be converged onto a single link.
IP Edge Router or Multi-Service Switching Platform N x GIGE
POTS Digital Loop Carrier
GIGE Over Fiber
IP
Dedicated Fiber Links
T1/E1 Broadband DLC
GIGE Over Fiber
Central Office
N x T1/E1
Central Office Switch (Class 5)
PSTN
CESoP
Figure 7 - Digital Loop Carrier using CESoP
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Zarlink Semiconductor Inc.
ZL50110/11/14
4.4 Remote Concentrator
Data Sheet
The remote concentrator application, shown in Figure 8, consists of a remote concentrators connected to the Central Office (CO) by a dedicated fiber link running Gigabit Ethernet (GE) or Ethernet over SONET (EoS) rather than by NxT1/E1 or DS3/E3. The remote concentrators provide both TDM service and native Ethernet service to the MTU/MDU. The ZL50110/11/14 is used to emulate TDM circuits over Ethernet by establishing CESoP connections between the remote concentrator and the CO. The native IP or Ethernet traffic is multiplexed with the CESoP traffic inside the remote concentrator and sent across the same GE connection to the CO. At the CO the native IP or Ethernet traffic is split from the CESoP connections at sent towards the packet network. Multiple T1/E1 CESoP connections from several remote concentrators are aggregated in the CO using a larger ZL50110/11/14 variant, converted back to TDM circuits, and connected to the PSTN through a higher bandwidth TDM circuit such as OC-3 or STM-1. The use of CESoP here allows the convergence of voice and data on a single access network based on Ethernet. This convergence on Ethernet, a packet technology, rather than SONET/SDH, a switched circuit technology, provides cost and operational savings.
Multi-Tenant / Multi-Dwelling Units
Ethernet 10/100 Mbps Remote Concentrator GIGE Over Fiber Nx GIGE
IP
T1/E1 Links
Ethernet 10/100 Mbps Remote Concentrator
Dedicated Fiber Links
Central Office
(Aggregation)
STM1- 4
GIGE Over Fiber
PSTN T1/E1 Links
T1/E1 Links
CESoP
Figure 8 - Remote Concentrator using CESoP
4.5
Cell Site Backhaul
The cell site backhaul application, shown in Figure 9, consists of 2G, 2.5G and 3G base stations, co-located at a cell site, connected to their respective 2G, 2.5G base station controllers and 3G radio network controller. The traditional leased T1/E1 lines between the cell site and the base station controllers is now replaced by a packet network such as fixed wireless or Gigabit Ethernet (GE) fiber, that may be owned by the carrier or accessed through a service provider. The ZL50110/11/14 would sit in a box either external to the base stations, or integrated in them, and would transparently carry multiple T1/E1s to the base station controllers using CESoP connections. At the base station controller location another ZL50110/11/14 would terminate the CESoP connection and provide the T1/E1 line to the controllers. The use of the ZL50110/11/14 would allow for lower cost transport between the two locations, due to the replacement of the leased T1/E1 line cost. The CESoP connection would allow the T1/E1 to meet the strict timing
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Zarlink Semiconductor Inc.
ZL50110/11/14
Data Sheet
requirements for 3G base stations. Each T1/E1 may be asynchronous should a service provider be backhauling T1/E1s from multiple carriers.
Co-Located Base Stations
3G Base Station ATM over T1/E1 ATM over T1/E1 3G Radio Network Controller DS3/ OC3
Packet Switched Network
2.5G Base Station ATM over T1/E1 ATM over T1/E1
CESoP
GIGE over Fiber TDM over T1/E1
CESoP
2.5G Base Station Controller
DS3/ OC3
2G Base Station
TDM over T1/E1
2G Base Station Controller
DS3/ OC3
CESoP
Figure 9 - Cell Site Backhaul using CESoP
4.6
Metro Ethernet Equipment
A Metro Ethernet service module, shown in Figure 10, supporting T1/E1 ports is shown at the board level using Zarlink's CESoP processors. The service module consists of three line cards and an uplink card connected to a packet backplane. The first line card supports up to 32 T1/E1 lines, containing up to 1024 DS0, for Nx64 kbps structured data transfer (SDT) CESoP connections. The T1/E1 lines are broken down into DS0 channels on an H.110 bus. The ZL50110/11/14 establishes CESoP connections, with each connection taking a number of DS0 channels from the H.110 bus. The third line card support up to 32 T1/E1 or 2 T3/E3 lines for private line unstructured data transfer (UDT) CESoP connections. The T1/E1 lines are not terminated on the card by are transparently packetized into individual CESoP connections by the ZL50110/11/14. The second line card support multiple 10/100/1000 Mbps Ethernet ports for native Internet, video and data service. The uplink card multiplexes the Ethernet traffic from the three cards, and uplinks the CESoP, Internet, video and data traffic to the packet switched network (PSN.)
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Structured, Synchronous CES Structured, Synchronous CES
H.110 / HMVIP BUS
T1/E1 LIUs
Data Sheet
Up to 32 T1/E1 or 1024 Channel
T1/E1 LIUs
Octal T1/E1 Framers MT9072
Up to 32 Streams
DPLL Output
CESoP Processor ZL50111
2 GE
Voice and Data Services
Ethernet Traffic
Ethernet Concentrator MVTX2601 MVTX2801
Gigabit Ethernet Switch MVTX2801
Ethernet PHYs Optical Interface & Drivers
Packet Switched Networks
Unstructured, Asynchronous CES Unstructured, Asynchronous CES
T3/E3 or T1/E1 LIU
2 GE
Up to 32 T1/E1 or 2 T3/E3
Per Port Clock Recovery
CESoP Processor ZL50111
T3/E3 or T1/E1 LIU
Figure 10 - Metro Ethernet Equipment using CESoP
5.0
Functional Description
The ZL50110/11/14 family provides the data-plane processing to enable constant bit rate TDM services to be carried over a packet switched network, such as an Ethernet, IP or MPLS network. The device segments the TDM data into user-defined packets, and passes it transparently over the packet network to be reconstructed at the far end. This has a number of applications, including emulation of TDM circuits and packet backplanes for TDM-based equipment.
Transparent data flow between TDM equipment
TDM equipment
constant bit rate TDM link
ZL5011x TDM-Packet conversion
interworking function
packet switched network
ZL5011x TDM-Packet conversion
interworking function
TDM equipment
constant bit rate TDM link
Figure 11 - ZL50110/11/14 Family Operation
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5.1 Block Diagram
Data Sheet
A diagram of the ZL50110/11/14 device is given in Figure 12, which shows the major data flows between functional components.
Motorola PowerQUICCTM Compatible
DMA Control
Host Interface
Admin.
Payload Assembly TDM Interface TDM Formatter
Central Task Manager
Packet Transmit
Protocol Engine
Packet Receive
Triple Packet Interface MAC
Clock Recovery
Memory Management Unit On-chip RAM and SSRAM Interface Controller
JTAG Test Controller
Data Flows Control Flows
Off-chip Packet Memory 0-8 MBytes SSRAM
JTAG Interface
Figure 12 - ZL50110/11/14 Data and Control Flows
5.2
Data and Control Flows
There are numerous combinations that can be implemented to pass data through the ZL50110/11/14 device depending on the application requirements. The Task Manager can be considered the central pivot, through which all flows must operate. The flow is determined by the Type field in the Task Message (see ZL50110/11/14 Programmers Model). Flow Number 1 2 3 4 5 6 7 8 9 Flow Through Device TDM to (TM) to PE to (TM) to PKT PKT to (TM) to PE to (TM) to TDM TDM to (TM) to PKT PKT to (TM) to TDM TDM to (TM) to CPU TDM to (TM) to PE to (TM) to CPU CPU to (TM) to TDM PKT to (TM) to CPU CPU to (TM) to PKT Table 21 - Standard Device Flows
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Zarlink Semiconductor Inc.
Triple 100 Mbps MII Fast Ethernet or Dual Redundant 1000 Mbps GMII/TBI Gigabit Ethernet
Up to 32 T1, 32 E1, 8 J2, 2 T3, 2 E3 or 1 STS-1 port H.110, H-MVIP, ST-BUS backplanes
ZL50110/11/14
Flow Number 101 111 Flow Through Device TDM to (TM) to TDM PKT to (TM) to PKT Table 21 - Standard Device Flows
1. This flow is for loopback test purposes only
Data Sheet
Each of the 11 data flows uses the Task Manager to route packet information to the next block or interface for onward transmission. This section describes the flows between the TDM interface, the packet interface and the Task Manager which are the main flow routes used in the ZL50110/11/14 family. For example, the TDM->TM flow is used in flow types 1, 3, 5, and 6, and the TM->PKT flow is used in flow types 1, 3, and 9.
5.3
TDM Interface
The ZL50110/11/14 family offers the following types of TDM service across the packet network: Service type Unstructured asynchronous Structured synchronous (N x 64 Kbps) TDM interface T1, E1, J2, E3, T3 and STS-1 T1, E1 and J2 Framed TDM data streams at 2.048 and 8.192 Mbps Interface type Bit clock in and out Data in and out Bit clock out Frame pulse out Data in and out Bit clock in Frame in Data in and out Interfaces to Line interface unit Framers TDM backplane (master) Framers TDM backplane (slave)
Table 22 - TDM Services Offered by the ZL50110/11/14 Family Unstructured services are fully asynchronous, and include full support for clock recovery on a per stream basis. Both adaptive and differential clock recovery mechanisms can be used. Structured services are synchronous, with all streams driven by a common clock and frame reference. These services can be offered in two ways: * * Synchronous master mode - the ZL50110/11/14 provides a common clock and frame pulse to all streams, which may be locked to an incoming clock or frame reference Synchronous slave mode - the ZL50110/11/14 accepts a common external clock and frame pulse to be used by all streams
In either mode, N x 64 Kbps trunking is supported as detailed in "Structured Payload Order" on page 55. In addition, it can be used with a variety of different protocols. It includes full support for the CESoPSN (Circuit Emulation Services over Packet Switched Networks) and SAToP (Structure-Agnostic Transport over Packet) protocols currently in development by the IETF's PWE3 (Pseudo-Wire Emulation Edge to Edge) working group.
5.3.1
TDM Interface Block
The TDM Access Interface consists of up to 32 streams (depending on variant), each with an input and an output data stream operating at either 1.544 Mbps or 2.048 Mbps. It contains two basic types of interface: unstructured clock and data, for interfacing directly to a line interface unit; or structured, framed data, for interfacing to a framer or TDM backplane.
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Data Sheet
Unstructured data is treated asynchronously, with every stream using its own clock. Clock recovery is provided on each output stream, to reproduce the TDM service frequency at the egress of the packet network. Structured data is treated synchronously, i.e., all data streams are timed by the same clock and frame references. These can either be supplied from an external source (slave mode) or generated internally using the on-chip stratum 3/4/4E DPLL (master mode).
5.3.2
Structured TDM Port Data Formats
The ZL50110/11/14 is programmable such that the frame/clock polarity and clock alignment can be set to any desired combination. Table 23 shows a brief summary of four different TDM formats; ST-BUS, H.110, H-MVIP, and Generic (synchronous mode only), for more information see the relevant specifications shown. There are many additional formats for TDM transmission not depicted in Table 23, but the flexibility of the port will cover almost any scenario. The overall data format is set for the entire TDM Interface device, rather than on a per stream basis. It is possible to control the polarity of the master clock and frame pulse outputs, independent of the chosen data format (used when operating in synchronous master mode). Number of channels per frame Nominal Frame Pulse Width (ns) ST-bus 2.048 2.048 8.192 H.110 H-MVIP 8.192 2.048 2.048 8.192 Generic 2.048 32 32 128 128 32 32 128 32 2.048 4.096 16.384 8.192 2.048 4.096 16.384 2.048 244 244 61 122 244 244 244 488 Negative Negative Negative Negative Negative Negative Negative Positive Rising Edge Falling Edge Falling Edge Rising edge Rising Edge Falling Edge Falling Edge Rising Edge Rising Edge Frame Boundary Alignment Standard clock frame pulse Straddles boundary Straddles boundary Straddles boundary Straddles boundary Straddles boundary Straddles boundary Straddles boundary Rising edge of clock Rising edge of clock ECTF H.110 H-MVIP Release 1.1a MSAN-126 Rev B (Issue 4) Zarlink
Data Format
Data Rate (Mbps)
Clock Freq. (MHz)
Frame Pulse Polarity
8.192
128
8.192
122
Positive
Table 23 - Some of the TDM Port Formats Accepted by the ZL50110/11/14 Family
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5.3.3 TDM Clock Structure
Data Sheet
The TDM interface can operate in two modes, synchronous for structured TDM data, and asynchronous for unstructured TDM data. The ZL50110/11/14 is capable of providing the TDM clock for either of the modes. The ZL50110/11/14 supports clock recovery in both synchronous and asynchronous modes of operation. In asynchronous operation each stream may have independent clock recovery.
5.3.3.1
Synchronous TDM Clock Generation
In synchronous mode all 32 streams will be driven by a common clock source. When the ZL50110/11/14 is acting as a master device, the source can either be the internal DPLL or an external PLL. In both cases, the primary and secondary reference clocks are taken from either two TDM input clocks, or two external clock sources driven to the chip. The input clocks are then divided down where necessary and sent either to the internal DPLL or to the output pins for connection to an external DPLL. The DPLL then provides the common clock and frame pulse required to drive the TDM streams. See "DPLL Specification" on page 66 for further details.
TDM_CLKi[31:0]
PRS
PRD
PLL_PRI PLL_SE C
DIV TDM_CLKiP SRS SRD
CLOCK
DIV TDM_CLKiS
Internal DPLL
FRAME
Figure 13 - Synchronous TDM Clock Generation When the ZL50110/11/14 is acting as a slave device, the common clock and frame pulse signals are taken from an external device providing the TDM master function.
5.3.3.2
Asynchronous TDM Clock Generation
Each stream uses a separate internal DCO to provide an asynchronous TDM clock output. The DCO can be controlled to recover the clock from the original TDM source depending on the timing algorithm used.
5.4
Payload Assembly
Data traffic received on the TDM Access Interface is sampled in the TDM Interface block, and synchronized to the internal clock. It is then forwarded to the payload assembly process. The ZL50110/11/14 Payload Assembler can handle up to 128 active packet streams or "contexts" simultaneously. Packet payloads are assembled in the format shown in Figure 14 on page 54. This meets the requirements of the CESoPSN standard under development in the IETF. Alternatively, packet payloads are assembled in the format shown in Figure 16 on page 56. This meets the requirements of the SAToP standard under development in the IETF When the payload has been assembled it is written into the centrally managed memory, and a task message is passed to the Task Manager.
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5.4.1 Structured Payload Operation
Data Sheet
In structured mode a context may contain any number of 64 kbps channels. These channels need not be contiguous and they may be selected from any input stream. Channels may be added or deleted dynamically from a context. This feature can be used to optimize bandwidth utilisation. Modifications to the context are synchronised with the start of a new packet. The fixed header at the start of each packet is added by the Packet Transmit block. This consists of up to 64 bytes, containing the Ethernet header, any upper layer protocol headers, and the two byte context descriptor field (see section below). The header is entirely user programmable, enabling the use of any protocol. The payload header and size must be chosen so that the overall packet size is not less than 64 bytes, the Ethernet standard minimum packet size. Where this is likely to be the case, the header or data must be padded (as shown in Figure 14 and Figure 16) to ensure the packet is large enough. This padding is added by the ZL50110/11/14 for most applications.
Ethernet Header Network Layers Header
(added by Packet Transmit)
may include VLAN tagging e.g. IPv4, IPv6, MPLS e.g. UDP, L2TP, RTP, CESoPSN, SAToP
Upper layers
(added by Protocol Engine)
Channel 1 Channel 2 Data for TDM Frame 1 Channel x Channel 1 Channel 2 Data for TDM Frame 2 TDM Payload Channel x
(constructed by Payload Assembler)
Channel 1 Channel 2 Data for TDM Frame n Channel x Static Padding
(if required to meet minimum payload size) may also be placed in the packet header
Ethernet FCS
Figure 14 - ZL50110/11/14 Packet Format - Structured Mode In applications where large payloads are being used, the payload size must be chosen such that the overall packet size does not exceed the maximum Ethernet packet size of 1518 bytes (1522 bytes with VLAN tags). Figure 14 shows the packet format for structured TDM data, where the payload is split into frames, and each frame concatenated to form the packet.
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5.4.1.1 Structured Payload Order
Data Sheet
Packets are assembled sequentially, with each channel placed into the packet as it arrives at the TDM Access Interface. A fixed order of channels is maintained (see Figure 15), with channel 0 placed before channel 1, which is placed before channel 2. It is this order that allows the packet to be correctly disassembled at the far end. A context must contain only unique channel numbers. As such a context that contains the same channel from different streams, for example channel 1 from stream 2 and channel 1 from stream 5, would not be permitted.
S tre a m 0 S tre a m 1 S tre a m 2
C hannel 0 C hannel 0 C hannel 0
C hannel 1 C hannel 1 C hannel 1
C hannel 2 C hannel 2 C hannel 2
C hannel 31 C hannel 31 C hannel 31
S tre a m 3 1
C hannel 0
C hannel 1
C hannel 2 C h a n n e l A ss e m b ly O rd e r
C hannel 31
Figure 15 - Channel Order for Packet Formation Each packet contains one or more frames of TDM data, in sequential order. This groups the selected channels for the first frame, followed by the same set of channels for the subsequent frame, and so on.
5.4.2
Unstructured Payload Operation
In unstructured mode, the payload is not split by defined frames or timeslots, so the packet consists of a continuous stream of data. Each packet contains a programmable number of octets, as shown in Figure 16. The number of octets in a packet need not be an integer number of frames. A typical value for N may be 192, as defined in the IETF PWE3 standard. For example, consider mapping the unstructured data of a 25 timeslot DS0 stream. The data for each T1 frame would normally consist of 193 bits, 192 data bits and 1 framing bit. If the payload consists of 24 octets it will be 1 bit short of a complete frames worth of data, if the payload consists of 25 octets it will be 7 bits over a complete frames worth of data. NOTE: No alignment of the octets with the T1 framing structure can be assumed.
Ethernet Header Network Layers
Header
(added by Packet Transmit)
Upper layers
(added by Protocol Engine)
may include VLAN tagging e.g. IPv4, IPv6, MPLS e.g. UDP, L2TP, RTP, CESoPSN, SAToP
N octets of data from unstructured stream NOTE: No frame or channel alignment
Octet 1 Octet 2 Octet N Static Padding Ethernet FCS
TDM Payload (constructed by Payload Assembler) 46 to 1500 bytes may also be placed in the
(if required to meet minimum payload size) packet header
Figure 16 - ZL50110/11/14 Packet Format - Unstructured Mode
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5.5 Protocol Engine
Data Sheet
In general, the next processing block for TDM packets is the Protocol Engine. This handles the data-plane requirements of the main higher level protocols (layers 4 and 5) expected to be used in typical applications of the ZL50110/11/14 family: UDP, RTP, L2TP, CESoPSN and SAToP. The Protocol Engine can add a header to the datagram containing up to 24 bytes. This header is largely static information, and is programmed directly by the CPU. It may contain a number of dynamic fields, including a length field, checksum, sequence number and a timestamp. The location, and in some cases the length of these fields is also programmable, allowing the various protocols to be placed at variable locations within the header.
5.6
Packet Transmission
Packets ready for transmission are queued to the switch fabric interface by the Queue Manager. Four classes of service are provided, allowing some packet streams to be prioritized over others. On transmission, the Packet Transmit block appends a programmable header, which has been set up in advance by the control processor. Typically this contains the data-link and network layer headers (layers 2 and 3), such as Ethernet, IP (versions 4 and 6) and MPLS. Packet Reception Incoming data traffic on the packet interface is received by the MACs. The well-formed packets are forwarded to a packet classifier to determine the destination. When a packet is successfully classified the destination can be the TDM interface, the LAN interface or the host interface. TDM traffic is then further classified to determine the context it is intended for. Each TDM interface context has an individual queue, and the TDM re-formatting process re-creates the TDM streams from the incoming packet streams. This queue is used as a jitter buffer, to absorb variation in packet delay across the network. The size of the jitter buffer can be programmed in units of TDM frames (i.e. steps of 125 s). There is also a queue to the host interface, allowing a traffic flow to the host CPU for processing. Again the host's DMA controller can be used to retrieve packet data and write it out into the CPU's own memory.
5.7
TDM Formatter
At the receiving end of the packet network, the original TDM data must be re-constructed from the packets received. This is known as re-formatting, and follows the reverse process from the Payload Assembler. The TDM Formatter plays out the packets in the correct sequence, directing each octet to the selected timeslot on the output TDM interface. When lost or late packets are detected, the TDM Formatter plays out underrun data for the same number of TDM frames as were included in the missing packet. Underrun data can either be the last value played out on that timeslot, or a pre-programmed value (e.g. 0xFF). If the packet subsequently turns up it is discarded. In this way, the end-to-end latency through the system is maintained at a constant value.
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6.0 Clock Recovery
Data Sheet
One of the main issues with circuit emulation is that the clock used to drive the TDM link is not necessarily linked into the central office reference clock, and hence may be any value within the tolerance defined for that service. The reverse link may also be independently timed, and operating at a slightly different frequency. In the plesiochronous digital hierarchy the difference in clock frequencies between TDM links is compensated for using bit stuffing techniques, allowing the clock to be accurately regenerated at the remote end of the carrier network. With a packet network, that connection between the ingress and egress frequency is broken, since packets are discontinuous in time. From Figure 5, the TDM service frequency fservice at the customer premises must be exactly reproduced at the egress of the packet network. The consequence of a long-term mismatch in frequency is that the queue at the egress of the packet network will either fill up or empty, depending on whether the regenerated clock is slower or faster than the original. This will cause loss of data and degradation of the service. The ZL50110/11/14 provides a per-stream clock recovery function to reproduce the TDM service frequency at the egress of the packet network. Two schemes are employed, depending on the availability of a common reference clock at each provider edge unit, within the ZL50110/11/14 - differential and adaptive. The clock recovery itself is performed by software in the external processor, with support from on-chip hardware to gather the required statistics.
6.1
Differential Clock Recovery
For applications where the wander characteristics of the recovered clock are very important, such as when the emulated circuit must be connected into the plesiochronous digital hierarchy (PDH), the ZL50110/11/14 also offers a differential clock recovery technique. This relies on having a common reference clock available at each provider edge point. In a differential technique, the timing of data packet formation is sent relative to the common reference clock. Since the same reference is available at the packet egress point and the packet size is fixed, the original service clock frequency can be recovered. This technique is unaffected by any low frequency components in the packet delay variation. The disadvantage is the requirement for a common reference clock at each end of the packet network, which could either be the central office TDM clock, or provided by a global position system (GPS) receiver.
PRS clock
Data
ZL5011x source node
Packets Packets
ZL5011x destination node Network Timestamp extraction DCO
Data
LIU
Source Clock
Timestamp generation
Dest'n Clock
LIU
Host CPU Timing recovery
Figure 17 - Differential Clock Recovery
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6.2 Adaptive Clock Recovery
Data Sheet
For applications where there is no common reference clock between provider edge units, an adaptive clock recovery technique is provided. This infers the clock rate of the original TDM service clock from the mean arrival rate of packets at the packet egress point. The disadvantage of this type of scheme is that, depending on the characteristics of the packet network, it may prove difficult to regenerate a clock that stays within the wander requirements of the plesiochronous digital hierarchy (specifically MTIE). The reason for this is that any variation in delay between packets will feed through as a variation in the frequency of the recovered clock. High frequency jitter can be filtered out, but any low frequency variation or wander is more difficult to remove without a very long time constant. This will in turn affect the ability of the system to lock to the original clock within an acceptable time. With no PRS clock the only information available to determine the TDM transmission speed is the average arrival rate of the packets, as shown in Figure 18. Timestamps representing the number of elapsed source clock periods may be included in the packet header, or information can be inferred from a known payload size at the destination. It is possible to maintain average buffer-fill levels at the destination, where an increase or decrease in the fill level of the buffer would require a change in transmission clock speed to maintain the average. Additionally, the buffer-fill depth can be altered independently, with no relation to the recovered clock frequency, to control TDM transmission latency.
Data
ZL5011x source node
Packets
ZL5011x destination node Network
Packets
Data
LIU
Source Clock
Dest'n Clock
LIU
DCO
Host CPU Queue monitor
Figure 18 - Adaptive Clock Recovery
6.3
SYSTEM_CLK Considerations
The qualitiy of the 100 MHz SYSTEM_CLK or the oscillator that drives SYSTEM_CLK directly impacts the adaptive clock recovery performance. Zarlink has a recommended oscillator and guidelines for the selection of an oscillator. Please review application note ZLAN-159 "External Component Selection" before choosing an oscillator.
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7.0
7.1
Data Sheet
System Features
Latency
The following lists the intrinsic processing latency of the ZL50110/11/14, regardless of the number of active channels or contexts. * * * * TDM to Packet transmission processing latency less than 125 s Packet to TDM transmission processing latency less than 250 s (unstructured) Packet to TDM transmission processing latency less than 250 s (structured, more than 16 channels in context) Packet to TDM transmission processing latency less than 375 s (structured, 16 or less channels in context)
End-to-end latency may be estimated as the transmit latency + packet network latency + receive latency. The transmit latency is the sum of the transmit processing and the number of frames per packet x 125 s. The receive latency is the sum of the receive processing and the delay through the jitter buffer which is programmed to compensate for packet network PDV. The ZL50110/11/14 is capable of creating an extremely low latency connection, with end to end delays of less than 0.5 ms, depending on user configuration.
7.2
Loopback Modes
The ZL50110/11/14 devices support loopback of the TDM circuits and the circuit emulation packets. TDM loopback is achieved by first packetizing the TDM circuit as normal via the TDM Interface and Payload Assembly blocks. The packetized data is then routed by the Task Manager back to the same TDM port via the TDM Formatter and TDM Interface. Loopback of the emulated services is achieved by redirecting classified packets from the Packet Receive blocks, back to the packet network. The Packet Transmit blocks are setup to strip the original header and add a new header directing the packets back to the source.
7.3
Host Packet Generation
The control processor can generate packets directly, allowing it to use the network for out-of-band communications. This can be used for transmission of control data or network setup information, e.g. routing information. The host interface can also be used by a local resource for network transmission of processed data. The device supports dual address DMA transfers of packets to and from the CPU memory, using the host's own DMA controller. Table 24 illustrates the maximum bandwidths achievable by an external DMA master. DMA Path ZL50110/11/14 to CPU only ZL50110/11/14 to CPU only CPU to ZL50110/11/14 only CPU to ZL50110/11/14 only Combined2 Combined2 Packet Size >1000 bytes 60 bytes >1000 bytes 60 bytes >1000 bytes 60 bytes Max Bandwidth Mbps1 50 6.7 60 43 58 (29 each way) 11 (5.5 each way)
Table 24 - DMA Maximum Bandwidths
Note 1: Note 2: Maximum bandwidths are the maximum the ZL50110/11/14 devices can transfer under host control, and assumes only minimal packet processing by the host. Combined figures assume the same amount of data is to be transferred each way.
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7.4 Loss of Service (LOS)
Data Sheet
During normal operation, a situation may arise where a Loss of Service occurs. This may be caused by a disruption in the transmission line due to engineering works or cable disconnection, for example. The locally detected LOS should be transferred across the emulated T1/E1 to the far end. The far end, in turn, should propagate AIS downstream. The handling of LOS over a CESoP connection is typically performed using (setting/clearing) the L bit in the CESoPSN or SAToP control word of the packet header. Refer to Application Note ZLAN-159, section 4.1 for details on a variety of different ways that LOS may be handled in an application.
7.5
External Memory Requirement
The ZL50110/11/14 family includes a large amount of on-chip memory, such that for most applications, external memory will not be required. However, for certain combinations of header size, packet size and jitter buffer size, there may be a requirement for external memory. Therefore the device allows the connection of up to 8 Mbytes of synchronous ZBT-SRAM. The following charts show how much memory is required by the ZL50111 (32 T1 streams) and the ZL50110 (8 T1 streams) for a variety of packet sizes (expressed in number of frames of TDM data) and jitter buffer sizes. It is assumed that each packet contains a full Ethernet/MPLS/MPLS/RTP/CESoPSN header.
External Memory Requirements for different packet sizes
32 T1 streams, with Ethernet/MPLS/MPLS/RTP/CESoPSN headers
8192
External memory requirement, KBytes
7168 6144 5120 4096 3072 2048 1024 0 4 8 16 32 64 128 256
1 frame packets 8 frame packets 16 frame packets 1 T3 stream (1 frame)
Jitter Buffer Size, ms
Figure 19 - External Memory Requirement for ZL50111
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Data Sheet
External Memory Requirements for different packet sizes
8 T1 streams, with Ethernet/MPLS/MPLS/RTP/CESoPSN headers
8192
External memory requirement, KBytes
7168 6144 5120 4096 3072 2048 1024 0 4 8 16 32 64 128 256
1 frame packets 8 frame packets 16 frame packets
Jitter Buffer Size, ms
Figure 20 - External Memory Requirement for ZL50110
7.6
GIGABIT Ethernet - Recommended Configurations
NOTE: In GMII/TBI mode only 1 GMAC port may be used. The second GMAC port is for redundancy purposes only. This section outlines connection methods for the ZL50110/11/14 in a Gigabit Ethernet environment recommended to ensure optimum performance. Two areas are covered: * * Central Ethernet Switch Redundant Ethernet Switch
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7.6.1 Central Ethernet Switch
Data Sheet
Network
Ethernet Switch
GMII
GMII
GMII
GMII
GMII
GMII
GMII
GMII
ZL5011x TDM
ZL5011x TDM
ZL5011x TDM
ZL5011x TDM
Figure 21 - Gigabit Ethernet Connection - Central Ethernet Switch TDM data and control packets are directed to the appropriate ZL50110/11/14 device through the Ethernet Switch. There is no limit on the number of ZL50110/11/14 devices that can be connected in this configuration.
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7.6.2 Redundant Ethernet Switch
Data Sheet
Network
Network
Ethernet Switch
Ethernet Switch
GMII
GMII
GMII
GMII
GMII
GMII
GMII
GMII
ZL5011x TDM
ZL5011x TDM
ZL5011x TDM
ZL5011x TDM
Figure 22 - Gigabit Ethernet Connection - Redundant Ethernet Switch The central Ethernet Switch configuration can be extended to include a redundant switch connected to the second ZL50110/11/14 GMII port. One port should be used for all the TDM-to-Packet and Packet-to-TDM data with the other port idle. If the current port fails then data must be transferred to the spare port.
7.7
Power Up sequence
To power up the ZL50110/11/14 the following procedure must be used: * * * The Core supply must never exceed the I/O supply by more than 0.5VDC Both the Core supply and the I/O supply must be brought up together The System Reset and, if used, the JTAG Reset must remain low until at least 100s after the 100 MHz system clock has stabilised. Note that if JTAG Reset is not used it must be tied low
This is illustrated in the diagram shown in Figure 23.
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I/O supply (3.3 V)
Data Sheet
VDD
<0.5 VDC
Core supply (1.8 V)
t
RST
t
> 100 s
SCLK
t
10 ns
Figure 23 - Powering Up the ZL50110/11/14
7.8
JTAG Interface and Board Level Test Features
The JTAG interface is used to access the boundary scan logic for board level production testing.
7.9
* * * *
External Component Requirements
Direct connection to PowerQUICCTM II (MPC8260) host processor and associated memory, but can support other processors with appropriate glue logic TDM Framers and/or Line Interface Units Ethernet PHY for each MAC port Optional ZBT-SRAM for extended packet memory buffer depth
7.10
* * * * * * *
Miscellaneous Features
System clock speed of 100 MHz Host clock speed of up to 66 MHz Debug option to freeze all internal state machines JTAG (IEEE1149) Test Access Port 3.3 V I/O Supply rail with 5 V tolerance 1.8 V Core Supply rail Fully compatible with MT90880/1/2/3 Zarlink product line
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7.11 7.11.1 Test Modes Operation Overview
Data Sheet
The ZL50110/11/14 family supports the following modes of operation.
7.11.1.1
System Normal Mode
This mode is the device's normal operating mode. Boundary scan testing of the peripheral ring is accessible in this mode via the dedicated JTAG pins. The JTAG interface is compliant with the IEEE Std. 1149.1-2001; Test Access Port and Boundary Scan Architecture. Each variant has it's own dedicated.bsdl file which fully describes it's boundary scan architecture.
7.11.1.2
System Tri-State Mode
All output and I/O output drivers are tri-stated allowing the device to be isolated when testing or debugging the development board.
7.11.2
Test Mode Control
The System Test Mode is selected using the dedicated device input bus TEST_MODE[2:0] as follows in Table 25. System Test Mode SYS_NORMAL_MODE SYS_TRI_STATE_MODE test_mode[2:0] 3'b000 3'b011
Table 25 - Test Mode Control
7.11.3
System Normal Mode
Selected by TEST_MODE[2:0] = 3'b000. As the test_mode[2:0] inputs have internal pull-downs this is the default mode of operation if no external pull-up/downs are connected. The GPIO[15:0] bus is captured on the rising edge of the external reset to provide internal bootstrap options. After the internal reset has been de-asserted the GPIO pins may be configured by the ADM module as either inputs or outputs.
7.11.4
System Tri-state Mode
Selected by TEST_MODE[2:0] = 3'b011. All device output and I/O output drivers are tri-stated.
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8.0 DPLL Specification
Data Sheet
The ZL50110/11/14 family incorporates an internal DPLL that meets Telcordia GR-1244-CORE Stratum 3 and Stratum 4/4E requirements, assuming an appropriate clock oscillator is connected to the system clock pin. It will meet the jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture range, phase change slope, holdover frequency and MTIE requirements for these specifications. In structured mode with the ZL50110/11/14 device operating as a master the DPLL is used to provide clock and frame reference signals to the internal and external TDM infrastructure. In structured mode, with the ZL50110/11/14 device operating as a slave, the DPLL is not used. All TDM clock generation is performed externally and the input streams are synchronised to the system clock by the TDM interface. The DPLL is not required in unstructured mode, where TDM clock and frame signals are generated by internal DCO's assigned to each individual stream.
8.1
Modes of Operation
It can be set into one of four operating modes: Locking mode, Holdover mode, Freerun mode and Powerdown mode.
8.1.1
Locking Mode (normal operation)
The DPLL accepts a reference signal from either a primary or secondary source, providing redundancy in the event of a failure. These references should have the same nominal frequencies but do not need to be identical as long as their frequency offsets meet the appropriate Stratum requirements. Each source is selected from any one of the available TDM input stream clocks (up to 32 on the ZL50111 variant), or from the external TDM_CLKiP (primary) or TDM_CLKiS (secondary) input pins, as illustrated in Figure 13 - on page 53. It is possible to supply a range of input frequencies as the DPLL reference source, depicted in Table 26. The PRD register Value is the number (in hexadecimal) that must be programmed into the PRD register within the DPLL to obtain the divided down frequency at PLL_PRI or PLL_SEC. Maximum Acceptable Input Wander tolerance (UI) (Note 2) 1 1023 1023 1023 1023 1023 1023 1 (on 64k Hz) 1 (on 64 kHz) 1 (on 64 kHz)
Source Input Frequency (MHz) 0.008 1.544 2.048 4.096 8.192 16.384 6.312 22.368 34.368 44.736 (Note 3)
Tolerance (ppm)
Divider Ratio
PRD/SRD Register Value (Hex) (Note 1) 1 1 1 1 1 1 1 AEC 219 2BB
Frequency at PLL_PRI or PLL_SEC (MHz) 0.008 1.544 2.048 4.096 8.192 16.384 6.312 0.008 0.064 0.064
30 130 50 50 50 50 30 20 20 20
1 1 1 1 1 1 1 2796 537 699
Table 26 - DPLL Input Reference Frequencies
Note 1: Note 2: Note 3: A PRD/SRD value of 0 will suppress the clock, and prevent it from reaching the DPLL. UI means Unit Interval - in this case periods of the time signal. So 1UI on a 64 kHz signal means 15.625 s, the period of the reference frequency. Similarly 1023UI on a 4.096 MHz signal means 250 s. This input frequency is supported with the use of an external divide by 2.
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Data Sheet
The maximum lock-in range can be programmed up to 372 ppm regardless of the input frequency. The DPLL will fail to lock if the source input frequency is absent, if it is not of approximately the correct frequency or if it is too jittery. See Section 8.7 for further details. Limitations depend on the users programmed values, so the DPLL must be programmed properly to meet Stratum 3, or Stratum 4/4E. The Application Program Interface (API) software that accompanies the ZL50110/11/14 family can be used to automatically set up the DPLL for the appropriate standard requirement. The DPLL lock-in range can be programmed using the Lock Range register (see ZL50110/11/14 Programmers Model document) in order to extend or reduce the capture envelope. The DPLL provides bit-error-free reference switching, meeting the specification limits in the Telcordia GR-1244-CORE standard. If Stratum 3 or Stratum 4/4E accuracy is not required, it is possible to use a more relaxed system clock tolerance. The DPLL output consists of three signals; a common clock (comclk), a double-rate common clock (comclkx2), and a frame reference (8 kHz). These are used to time the internal TDM Interface, and hence the corresponding TDM infrastructure attached to the interface. The output clock options are either 2.048 Mbps (comclkx2 at 4.096 Mbps) or 8.192 Mbps (comclkx2 at 16.384 Mbps), determined by setup in the DPLL control register. The frame pulse is programmable for polarity and width.
8.1.2
Holdover Mode
In the event of a reference failure resulting in an absence of both the primary and secondary source, the DPLL automatically reverts to Holdover mode. The last valid frequency value recorded before failure can be maintained within the Stratum 3 limits of 0.05 ppm. The hold value is wholly dependent on the drift and temperature performance of the system clock. For example, a 32 ppm oscillator may have a temperature coefficient of 0.1 ppm/C. Thus a 10C ambient change since the DPLL was last in the Locking mode will change the holdover frequency by an additional 1 ppm, which is much greater than the 0.05 ppm Stratum 3 specification. If the strict target of Stratum 3 is not required, a less restrictive oscillator can be used for the system clock. Holdover mode is typically used for a short period of time until network synchronisation is re-established.
8.1.3
Freerun Mode
In freerun mode the DPLL is programmed with a centre frequency, and can output that frequency within the Stratum 3 limits of 4.6 ppm. To achieve this the 100 MHz system clock must have an absolute frequency accuracy of 4.6 ppm. The centre frequency is programmed as a fraction of the system clock frequency.
8.1.4
Powerdown Mode
It is possible to "power down" the DPLL when it is not in use. For example, an unstructured TDM system, or use of an external DPLL would mean the internal DPLL could be switched off, saving power. The internal registers can still be accessed while the DPLL is powered down.
8.2
Reference Monitor Circuit
There are two identical reference monitor circuits, one for the primary and one for the secondary source. Each circuit will continually monitor its reference, and report the references validity. The validity criteria depends on the frequency programmed for the reference. A reference must meet all the following criteria to maintain validity: * The "period in specified range" check is performed regardless of the programmed frequency. Each period must be within a range, which is programmable for the application. Refer to the ZL50110/11/14 programmers model for details. If the programmed frequency is 1.544 MHz or 2.048 MHz, the "n periods in specified range" check will be performed. The time taken for n cycles must be within a programmed range, typically with n at 64, the time taken for consecutive cycles must be between 62 and 66 periods of the programmed frequency.
*
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Data Sheet
The fail flags are independent of the preferred option for primary or secondary operation, will be asserted in the event of an invalid signal regardless of mode.
8.3
Locking Mode Reference Switching
When the reference source the DPLL is currently locking to becomes invalid, the DPLL's response depends on which one of the failure detect modes has been chosen: autodetect, forced primary, or forced secondary. One of these failure detect modes must be chosen via the FDM1:0 bits of the DOM register. After a device reset via the SYSTEM_RESET pin, the autodetect mode is selected. In autodetect mode (automatic reference switching) if both references are valid the DPLL will synchronise to the preferred reference. If the preferred reference becomes unreliable, the DPLL continues driving its output clock in a stable holdover state until it makes a switch to the backup reference. If the preferred reference recovers, the DPLL makes a switch back to the preferred reference. If necessary, the switch back can be prevented by changing the preferred reference using the REFSEL bit in the DOM register, after the switch to the backup reference has occurred. If both references are unreliable, the DPLL will drive its output clock using the stable holdover values until one of the references becomes valid. In forced primary mode, the DPLL will synchronise to the primary reference only. The DPLL will not switch to the secondary reference under any circumstances including the loss of the primary reference. In this condition, the DPLL remains in holdover mode until the primary reference recovers. Similarly in forced secondary mode, the DPLL will synchronise to the secondary reference only, and will not switch to the primary reference. Again, a failure of the secondary reference will cause the DPLL to enter holdover mode, until such time as the secondary reference recovers. The choice of preferred reference has no effect in these modes. When a conventional PLL is locked to its reference, there is no phase difference between the input reference and the PLL output. For the DPLL, the input references can have any phase relationship between them. During a reference switch, if the DPLL output follows the phase of the new reference, a large phase jump could occur. The phase jump would be transferred to the TDM outputs. The DPLL's MTIE (Maximum Time Interval Error) feature preserves the continuity of the DPLL output so that it appears no reference switch had occurred. The MTIE circuit is not perfect however, and a small Time Interval Error is still incurred per reference switch. To align the DPLL output clock to the nearest edge of the selected input reference, the MTIE reset bit (MRST bit in the DOM register) can be used. Unlike some designs, switching between references which are at different nominal frequencies do not require intervention such as a system reset.
8.4
Locking Range
The locking range is the input frequency range over which the DPLL must be able to pull into synchronization and to maintain the synchronization. The locking range is programmable up to 372 ppm. Note that the locking range relates to the system clock frequency. If the external oscillator has a tolerance of -100 ppm, and the locking range is programmed to 200 ppm, the actual locking range is the programmed value shifted by the system clock tolerance to become -300 ppm to +100 ppm.
8.5
Locking Time
The Locking Time is the time it takes the synchroniser to phase lock to the input signal. Phase lock occurs when the input and output signals are not changing in phase with respect to each other (not including jitter). Locking time is very difficult to determine because it is affected by many factors including: * * initial input to output phase difference initial input to output frequency difference
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* * DPLL Loop Filter DPLL Limiter (phase slope)
Data Sheet
Although a short phase lock time is desirable, it is not always achievable due to other synchroniser requirements. For instance, better jitter transfer performance is obtained with a lower frequency loop filter which increases locking time; and a better (smaller) phase slope performance will increase locking time. Additionally, the locking time is dependent on the p_shift value. The DPLL Loop Filter and Limiter have been optimised to meet the Telcordia GR-1244-CORE jitter transfer and phase alignment speed requirements. The phase lock time is guaranteed to be no greater than 30 seconds when using the recommended Stratum 3 and Stratum 4/4E register settings.
8.6
Lock Status
The DPLL has a Lock Status Indicator and a corresponding Lock Change Interrupt. The response of the Lock Status Indicator is a function of the programmed Lock Detect Interval (LDI) and Lock Detect Threshold (LDT) values in the dpll_ldetect register. The LDT register can be programmed to set the jitter tolerance level of the Lock Status Indicator. To determine if the DPLL has achieved lock the Lock Status Indicator must be high for a period of at least 30 seconds. When the DPLL loses lock the Lock Status Indicator will go low after LDI x 125 s.
8.7
Jitter
The DPLL is designed to withstand, and improve inherent jitter in the TDM clock domain.
8.7.1
Acceptance of Input Wander
For T1(1.544 MHz), E1(2.048 MHz) and J2(6.312 MHz) input frequencies, the DPLL will accept a wander of up to 1023UIpp at 0.1 Hz to conform with the relevant specifications. For the 8 kHz (frame rate) and 64 kHz (the divided down output for T3/E3) input frequencies, the wander acceptance is limited to 1 UI (0.1 Hz). This principle is illustrated in Table 26.
8.7.2
Intrinsic Jitter
Intrinsic jitter is the jitter produced by a synchronizer and measured at its output. It is measured by applying a jitter free reference signal to the input of the device, and measuring its output jitter. Intrinsic jitter may also be measured when the device is in a non synchronizing mode such as free running or holdover, by measuring the output jitter of the device. Intrinsic jitter is usually measured with various band-limiting filters, depending on the applicable standards. The intrinsic jitter in the DPLL is reduced to less than 1 ns p-p1 by an internal Tapped Delay Line (TDL). The DPLL can be programmed so that the output clock meets all the Stratum 3 requirements of Telcordia GR-1244-CORE. Stratum 4/4E is also supported.
8.7.3
Jitter Tolerance
Jitter tolerance is a measure of the ability of a PLL to operate properly without cycle slips (i.e. remain in lock and/or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied jitter magnitude and the jitter frequency depends on the applicable standards. The DPLL's jitter tolerance can be programmed to meet Telcordia GR-1244-CORE DS1 reference input jitter tolerance requirements.
1. There are 2 exceptions to this. a) When reference is 8 kHz, and reference frequency offset relative to the master is small, jitter up to 1 master clock period is possible, i.e. 10 ns p-p. b) In holdover mode, if a huge amount of jitter had been present prior to entering holdover, then an additional 2 ns p-p is possible.
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8.7.4 Jitter Transfer
Data Sheet
Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than larger ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter signals (e.g. 75% of the specified maximum jitter tolerance). The internal DPLL is a first order type 2 component, so a frequency offset doesn't result in a phase offset. Stratum 3 requires a -3 dB frequency of less than 3 Hz. The nature of the filter results in some peaking, resulting in a -3dB frequency of 1.9 Hz and a 0.08 dB peak with a system clock frequency of 100 MHz assuming a p_shift value of 2. The transfer function is illustrated in Figure 24 and in more detail in Figure 25. Increasing the p_shift value increases the speed the DPLL will lock to the required frequency and reduces the peak, but also reduces the tolerance to jitter - so the p_shift value must be programmed correctly to meet Stratum 3 or Stratum 4/4E jitter transfer characteristics. This is done automatically in the API.
8.8
Maximum Time Interval Error (MTIE)
In order to meet several standards requirements, the phase shift of the DPLL output must be controlled. A potential phase shift occurs every time the DPLL is re-arranged by changing reference source signal, or the mode. In order to meet the requirements of Stratum 3, the DPLL will shift phase by no more than 20 ns per re-arrangement. Additionally the speed at which the change occurs is also critical. A large step change in output frequency is undesirable. The rate of change is programmable using the skew register, up to a maximum of 15.4 ns / 125 s (124 ppm).
Figure 24 - Jitter Transfer Function
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Data Sheet
Figure 25 - Jitter Transfer Function - Detail
9.0
Memory Map and Register Definitions
All memory map and register definitions are included in the ZL50110/11/14 Programmers Model document.
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10.0 DC Characteristics
Data Sheet
Absolute Maximum Ratings*
Parameter I/O Supply Voltage Core Supply Voltage PLL Supply Voltage Input Voltage Input Voltage (5 V tolerant inputs) Continuous current at digital inputs Continuous current at digital outputs Package power dissipation Storage Temperature Symbol VDD_IO VDD_CORE VDD_PLL VI VI_5V IIN IO PD TS Min. -0.5 -0.5 -0.5 -0.5 -0.5 -55 Max. 5.0 2.5 2.5 VDD + 0.5 7.0 10 15 3 +125 Units V V V V V mA mA W C
* Exceeding these figures may cause permanent damage. Functional operation under these conditions is not guaranteed. Voltage measurements are with respect to ground (VSS) unless otherwise stated. * The core and PLL supply voltages must never be allowed to exceed the I/O supply voltage by more than 0.5 V during power-up. Failure to observe this rule could lead to a high-current latch-up state, possibly leading to chip failure, if sufficient cross-supply current is available. To be safe ensure the I/O supply voltage supply always rises earlier than the core and PLL supply voltages.
Recommended Operating Conditions Characteristics Operating Temperature Junction temperature Positive Supply Voltage, I/O Positive Supply Voltage, Core Positive Supply Voltage, Core Input Voltage Low - all inputs Input Voltage High Input Voltage High, 5V tolerant inputs Symbol TOP TJ VDD_IO VDD_CORE VDD_PLL VIL VIH VIH_5V Min. -40 -40 3.0 1.65 1.65 2.0 2.0 Typ. 25 3.3 1.8 1.8 Max. +85 125 3.6 1.95 1.95 0.8 VDD_IO 5.5 Units C C V V V V V V Test Condition
Typical figures are at 25C and are for design aid only, they are not guaranteed and not subject to production testing. Voltage measurements are with respect to ground (VSS) unless otherwise stated.
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Data Sheet
DC Electrical Characteristics - Typical characteristics are at 1.8 V core, 3.3 V I/O, 25C and typical processing. The min. and
max. values are defined over all process conditions, from -40 to 125C junction temperature, core voltage 1.65 to 1.95 V and I/O voltage 3.0 and 3.6 V unless otherwise stated.
Characteristics Input Leakage Output (High impedance) Leakage Input Capacitance Output Capacitance Pullup Current Pullup Current, 5 V tolerant inputs Pulldown Current Pulldown Current, 5 V tolerant inputs Core 1.8 V supply current PLL 1.8 V supply current I/O 3.3 V supply current
Note 1: Note 2:
Symbol ILEIP ILEOP CIP COP IPU IPU_5V IPD IPD_5V IDD_CORE IDD_PLL IDD_IO
Min.
Typ.
Max. 1 2
Units. A A pF pF A A A A
Test Condition No pull up/down VDD_IO = 3.6 V No pull up/down VDD_IO = 3.6 V
1 4 -27 -110 27 110 950 1.30 120
Input at 0 V Input at 0 V Input at VDD_IO Input at VDD_IO Note 1,2
mA mA mA
Note 1,2
The IO and Core supply current worst case figures apply to different scenarios, e.g., internal or external memory and can not simply be summed for a total figure. For a clearer indication of power consumption, please refer to Section 12.0. Worst case assumes the maximum number of active contexts and channels, i.e., 128 contexts/1024 channels. Figures are for the ZL50111. For an indication of power consumption by the ZL50110 and ZL50114, please refer to Section 12.0 and choose the appropriate memory configuration and number of contexts.
Input Levels Characteristics Input Low Voltage Input High Voltage Positive Schmitt Threshold Negative Schmitt Threshold Output Levels Characteristics Output Low Voltage Symbol VOL Min. Typ. Max. 0.4 Units V Test Condition IOL = 6 mA. IOL = 12 mA for packet interface (m*) pins and GPIO pins. IOL = 24 mA for LED pins. IOH = 6 mA. IOH = 12 mA for packet interface (m*) pins and GPIO pins. IOH = 24 mA for LED pins. Symbol VIL VIH VT+ VT2.0 1.6 1.2 Min. Typ. Max. 0.8 Units V V V V Test Condition
Output High Voltage
VOH
2.4
V
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11.0
11.1
Data Sheet
AC Characteristics
TDM Interface Timing - ST-BUS
The TDM Bus either operates in Slave mode, where the TDM clocks for each stream are provided by the device sourcing the data, or Master mode, where the TDM clocks are generated from the ZL50110/11/14.
11.1.1
ST-BUS Slave Clock Mode
TDM ST-BUS Slave Timing Specification Data Format ST-BUS 8.192 Mbps mode ST-BUS 2.048 Mbps mode All Modes Parameter TDM_CLKi Period TDM_CLKi High TDM_CLKi Low TDM_CLKi Period TDM_CLKi High TDM_CLKi Low TDM_F0i Width 8.192 Mbps 2.048 Mbps TDM_F0i Setup Time Symbol tC16IP tC16IH tC16IL tC4IP tC4IH tC4IL tFOIW 50 200 tFOIS 5 300 ns With respect to TDM_CLKi falling edge With respect to TDM_CLKi falling edge With respect to TDM_CLKi Load CL = 50 pF With respect to TDM_CLKi With respect to TDM_CLKi Min. 54 27 27 110 110 Typ. 60 244.1 Max. 66 33 33 134 134 Units ns ns ns ns ns ns ns Notes
TDM_F0i Hold Time
tFOIH
5
-
-
ns
TDM_STo Delay
tSTOD
1
-
20
ns
TDM_STi Setup Time TDM_STi Hold Time
tSTIS tSTIH
5 5
-
-
ns ns
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Data Sheet
In synchronous mode the clock must be within the locking range of the DPLL to function correctly ( 245 ppm). In asynchronous mode, the clock may be any frequency.
Channel 127 bit 1 TDM_CKLI
Channel 127 bit 0
Channel 0 bit 7 tC16IP
Channel 0 bit 6
tFOIH tFOIS TDM_F0i tSTIH tSTIS TDM_STi tSTOD Channel 127 bit 0 tSTIH tSTIS tSTIH tSTIS
Ch0 bit7
TDM_STo
Channel 127 bit 1
tSTOD Channel 0 bit 7
tSTOD
Figure 26 - TDM ST-BUS Slave Mode Timing at 8.192 Mbps
Channel 31 Bit 0
Channel 0 Bit 7 tC2IP
Channel 0 Bit 6
TDM_CLKI (2.048 MHz) tC4IP TDM_CLKI (4.096 MHz) tFOIH tFOIS TDM_F0i tFOIW tSTIH tSTIS TDM_STi tSTOD TDM_STo Ch 31 Bit 0 Ch 0 Bit 7 tSTOD Ch 0 Bit 6
Figure 27 - TDM ST-BUS Slave Mode Timing at 2.048 Mbps
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11.1.2 ST-BUS Master Clock Mode
Parameter TDM_CLKo Period TDM_CLKo High TDM_CLKo Low TDM_CLKo Period TDM_CLKo High TDM_CLKo Low TDM_F0o Delay Symbol tC16OP tC16OH tC16OL tC4OP tC4OH tC4OL tFOD Min. 54.0 23.0 23.0 237.0 115.0 115.0 Typ. 61.0 244.1 Max. 68.0 37.0 37.0 251.0 129.0 129.0 25 Units ns ns ns ns ns ns ns
Data Sheet
Data Format ST-BUS 8.192 Mbps mode ST-BUS 2.048 Mbps mode All Modes
Notes
With respect to TDM_CLKo falling edge With respect to TDM_CLKo falling edge With respect to TDM_CLKo falling edge With respect to TDM_CLKo With respect to TDM_CLKo
TDM_STo Delay Active-Active TDM_STo Delay Active to HiZ and HiZ to Active TDM_STi Setup Time TDM_STi Hold Time
tSTOD
-
-
5
ns
tDZ, tZD
-
-
33
ns
tSTIS tSTIH
5 5
-
-
ns ns
Table 27 - TDM ST-BUS Master Timing Specification
Channel 127 Bit 0 TDM_CLKO tFOD TDM_F0o tSTIH tSTIS TDM_STi B0
Channel 0 Bit 7 tC16OP
Channel 0 Bit 6
tFOD tSTIH tSTIS B7 tSTOD tSTOD Ch 0 Bit 6 B6
TDM_STo
Ch 127 Bit 0
Ch 0 Bit 7
Figure 28 - TDM Bus Master Mode Timing at 8.192 Mbps
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Data Sheet
Channel 31 Bit 0 TDM_CLKO (2.048 MHz)
Channel 0 Bit 7 tC2OP
Channel 0 Bit 6
tC4OP TDM_CLKO (4.096 MHz) tFOD TDM_F0o tSTIH tSTIS TDM_STi tSTOD TDM_STo Ch 31 Bit 0 Ch 0 Bit 7 tSTOD Ch 0 Bit 6 tFOD
Figure 29 - TDM Bus Master Mode Timing at 2.048 Mbps
11.2
TDM Interface Timing - H.110 Mode
These parameters are based on the H.110 Specification from the Enterprise Computer Telephony Forum (ECTF) 1997. Parameter TDM_C8 Period TDM_C8 High TDM_C8 Low TDM_D Output Delay TDM_D Output to HiZ TDM_D HiZ to Output TDM_D Input Delay to Valid TDM_D Input Delay to Invalid TDM_FRAME width TDM_FRAME setup TDM_FRAME hold Phase Correction Symbol tC8P tC8H tC8L tDOD tDOZ tZDO tDV tDIV tFP tFS tFH F Min. 122.066- 63- 63- 0 0 0 102 90 45 45 0 Typ. 122 122 Max. 122.074+ 69+ 69+ 11 33 11 83 112 180 90 90 10 Units ns ns ns ns ns ns ns ns ns ns ns ns Note 6 Load - 12 pF Load - 12 pF Note 3 Load - 12 pF Note 3 Note 4 Note 4 Note 5 Notes Note 1 Note 2
Table 28 - TDM H.110 Timing Specification
Note Note Note Note Note 1: 2: 3: 4: 5: TDM_C8 and TDM_FRAME signals are required to meet the same timing standards and so are not defined independently. TDM_C8 corresponds to pin TDM_CLKi. tDOZ and t ZDO apply at every time-slot boundary. Refer to H.110 Standard from Enterprise Computer Telephony Forum (ECTF) for the source of these numbers. The TDM_FRAME signal is centred on the rising edge of TDM_C8. All timing measurements are based on this rising edge point; TDM_FRAME corresponds to pin TDM_F0i. Phase correction () results from DPLL timing corrections.
Note 6:
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Data Sheet
Ts 127 Bit 8 tC8H
Ts 0 Bit 1 tC8L tC8P
Ts 0 Bit 2
TDM_C8 tFS tFP TDM_FRAME tDIV tDV TDM_D Input tZDO tDOZ TDM_D Output Ts 127 Bit 8 Ts 0 Bit 1 tDOD Ts 0 Bit 2 tFH
Figure 30 - H.110 Timing Diagram
11.3
TDM Interface Timing - H-MVIP
These parameters are based on the Multi-Vendor Integration Protocol (MVIP) specification for an H-MVIP Bus, Release 1.1a (1997). Positive transitions of TDM_C2 are synchronous with the falling edges of TDM_C4 and TDM_C16. The signals TDM_C2, TDM_C4 and TDM_C16 correspond with pins TDM_CLKi. The signals TDM_F0 correspond with pins TDM_F0i. The signals TDM_HDS correspond with pins TDM_STi and TDM_STo. Parameter TDM_C2 Period TDM_C2 High TDM_C2 Low TDM_C4 Period TDM_C4 High TDM_C4 Low TDM_C16 Period TDM_C16 High TDM_C16 Low TDM_HDS Output Delay TDM_HDS Output Delay TDM_HDS Output to HiZ TDM_HDS Input Setup TDM_HDS Input Hold Symbol tC2P tC2H tC2L tC4P tC4H tC4L tC16P tC16H tC16L tPD tPD tHZD tS tH Min. 487.8 220 220 243.9 110 110 60.9 30 30 30 30 Typ. 488.3 244.1 61.0 Max. 488.8 268 268 244.4 134 134 61.1 31 31 30 100 30 0 0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns At 8.192 Mbps At 2.048 Mbps Notes
Table 29 - TDM H-MVIP Timing Specification
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Parameter TDM_F0 width TDM_F0 setup TDM_F0 hold Symbol tFW tFS tFH Min. 200 50 50 Typ. 244 Max. 300 150 150 Units ns ns ns
Data Sheet
Notes
Table 29 - TDM H-MVIP Timing Specification (continued)
Ts 127 Bit 7 tC16P tC16L TDM_C16 tFS tFW TDM_F0 tFH
Ts 0 Bit 0 tC16H
Ts 0 Bit 1
tH tS TDM_HDS Input tPD tHZD TDM_HDS Output Ch 127 Bit 7 Ch 0 Bit 0
Figure 31 - TDM - H-MVIP Timing Diagram for 16 MHz Clock (8.192 Mbps)
11.4
TDM LIU Interface Timing
The TDM Interface can be used to directly drive into a Line Interface Unit (LIU). The interface can work in this mode with E1, DS1, J2, E3 and DS3. The frame pulse is not present, just data and clock is transmitted and received. Table 30 shows timing for DS3, which would be the most stringent requirement. Parameter TDM_TXCLK Period TDM_TXCLK High TDM_TXCLK Low TDM_RXCLK Period TDM_RXCLK High TDM_RXCLK Low TDM_TXDATA Output Delay TDM_RXDATA Input Setup TDM_RXDATA Input Hold Symbol tCTP tCTH tCTL tCRP tCRH tCRL tPD tS tH 9.0 9.0 3 6 3 10 6.7 6.7 22.353 Min. Typ. 22.353 Max. Units ns ns ns ns ns ns ns ns ns DS3 clock Notes DS3 clock
Table 30 - TDM - LIU Structured Transmission/Reception
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Data Sheet
tCTP TDM_TXCLK
tCTH tCTL
tPD TDM_TXDATA tCRH tCRP TDM_RXCLK tS TDM_RXDATA tH tCRL
Figure 32 - TDM-LIU Structured Transmission/Reception
11.5
PAC Interface Timing
Parameter Symbol tCPP tCSP Min. 10 10 Typ. Max. Units ns ns Notes
TDM_CLKiP High / Low Pulsewidth TDM_CLKiS High / Low Pulsewidth
Table 31 - PAC Timing Specification
11.6
Packet Interface Timing
Data for the MII/GMII/TBI packet switching is based on Specification IEEE Std. 802.3 - 2000.
11.6.1
MII Transmit Timing
100 Mbps Parameter Symbol Min. Typ. 40 Max. 26 26 5 5 25 25 ns ns ns ns ns ns ns Load = 25 pF Load = 25 pF tCC tCHI tCLO tCR tCF tDV tEV 14 14 1 1 Units Notes
TXCLK period TXCLK high time TXCLK low time TXCLK rise time TXCLK fall time TXCLK rise to TXD[3:0] active delay (TXCLK rising edge) TXCLK to TXEN active delay (TXCLK rising edge)
Table 32 - MII Transmit Timing - 100 Mbps
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100 Mbps Parameter TXCLK to TXER active delay (TXCLK rising edge) Symbol Min. tER 1 Typ. Max. 25 ns Units
Data Sheet
Notes Load = 25 pF
Table 32 - MII Transmit Timing - 100 Mbps
tCC TXCLK tEV TXEN tDV TXD[3:0] tER TXER tER
tCL
tCH
tEV
Figure 33 - MII Transmit Timing Diagram
11.6.2
MII Receive Timing
100 Mbps Parameter Symbol Min. Typ. 40 20 20 Max. 26 26 5 5 ns ns ns ns ns ns ns ns ns ns ns tCC tCH tCL tCR tCF tDS tDH tDVS tDVH tERS tERH 14 14 10 5 10 5 10 5 Units Notes
RXCLK period RXCLK high wide time RXCLK low wide time RXCLK rise time RXCLK fall time RXD[3:0] setup time (RXCLK rising edge) RXD[3:0] hold time (RXCLK rising edge) RXDV input setup time (RXCLK rising edge) RXDV input hold time (RXCLK rising edge) RXER input setup time (RXCL edge) RXER input hold time (RXCLK rising edge)
Table 33 - MII Receive Timing - 100 Mbps
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Data Sheet
tCC RXCLK tDVS RXDV tDH tDS RXD[3:0] tERH tERS RXER
tCLO
tCHI
tDVH
Figure 34 - MII Receive Timing Diagram
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11.6.3 GMII Transmit Timing
1000 Mbps Parameter GTXCLK period GTXCLK high time GTXCLK low time GTXCLK rise time GTXCLK fall time GTXCLK rise to TXD[7:0] active delay GTXCLK rise to TXEN active delay GTXCLK rise to TXER active delay Symbol Min. tGC tGCH tGCL tGCR tGCF tDV tEV tER 7.5 2.5 2.5 1.5 2 1 Typ. Max. 8.5 1 1 6 6 6 ns ns ns ns ns ns ns ns Units
Data Sheet
Notes
Load = 25 pF Load = 25 pF Load = 25 pF
Table 34 - GMII Transmit Timing - 1000 Mbps
tCC GTXCLK tEV TXEN tDV TXD[3:0] tER TXER tER
tCL
tCH
tEV
Figure 35 - GMII Transmit Timing Diagram
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11.6.4 GMII Receive Timing
1000 Mbps Parameter RXCLK period RXCLK high wide time RXCLK low wide time RXCLK rise time RXCLK fall time RXD[7:0] setup time (RXCLK rising edge) RXD[7:0] hold time (RXCLK rising edge) RXDV setup time (RXCLK rising edge) RXDV hold time (RXCLK rising edge) RXER setup time (RXCLK rising edge) RXER hold time (RXCLK rising edge) Symbol Min. tCC tCH tCL tCR tCF tDS tDH tDVS tDVH tERS tERH 7.5 2.5 2.5 2 1 2 1 2 1 Typ. Max. 8.5 1 1 ns ns ns ns ns ns ns ns ns ns ns Units
Data Sheet
Notes
Table 35 - GMII Receive Timing - 1000 Mbps
tCC RXCLK tDVS RXDV tDH tDS RXD[7:0] tERH tERS RXER
tCLO
tCHI
tDVH
Figure 36 - GMII Receive Timing Diagram
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11.6.5 TBI Interface Timing
1000 Mbps Parameter GTXCLK period GTXCLK high wide time GTXCLK low wide time TXD[9:0] Output Delay (GTXCLK rising edge) RCB0/RBC1 period RCB0/RBC1 high wide time RCB0/RBC1 low wide time RCB0/RBC1 rise time RCB0/RBC1 fall time RXD[9:0] setup time (RCB0 rising edge) RXD[9:0] hold time (RCB0 rising edge) REFCLK period REFCLK high wide time REFCLK low wide time Symbol Min. tGC tGH tGL tDV tRC tRH tRL tRR tRF tDS tDH tFC tFH tFL 7.5 2.5 2.5 1 15 5 5 2 1 7.5 2.5 2.5 Typ. 16 Max. 8.5 6 17 2 2 8.5 ns ns ns ns ns ns ns ns ns ns ns ns ns Units
Data Sheet
Notes
Load = 25 pF
Table 36 - TBI Timing - 1000 Mbps
tGC GTXCLK tDV /S/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /T/ /R/
TXD[9:0] Signal_Detect
/I/
/I/
Figure 37 - TBI Transmit Timing Diagram
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tRC RBC1 tRC RBC0 tDH RXD[9:0] Signal_Detect /I/ /S/ /D/ /D/ /D/ tDS /D/ /D/ /D/ /D/ /D/ tDS /D/ /D/ /D/ tDH /D/ /T/ /R/
Data Sheet
/I/
Figure 38 - TBI Receive Timing Diagram
11.6.6
Management Interface Timing
The management interface is common for all inputs and consists of a serial data I/O line and a clock line. Parameter M_MDC Clock Output period M_MDC high M_MDC low M_MDC rise time M_MDC fall time M_MDIO setup time (MDC rising edge) M_MDIO hold time (M_MDC rising edge) M_MDIO Output Delay (M_MDC rising edge) Symbol tMP tMHI tMLO tMR tMF tMS tMH tMD Min. 1990 900 900 10 10 1 Typ. 2000 1000 1000 Max. 2010 1100 1100 5 5 300 Units ns ns ns ns ns ns ns ns Note 1 Note 1 Note 2 Notes Note 1
Table 37 - MAC Management Timing Specification
Note 1: Note 2: Refer to Clause 22 in IEEE802.3 (2000) Standard for input/output signal timing characteristics. Refer to Clause 22C.4 in IEEE802.3 (2000) Standard for output load description of MDIO.
tMHI M_MDC tMS M_MDIO tMH
tMLO
Figure 39 - Management Interface Timing for Ethernet Port - Read
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tMP M_MDC tMD M_MDIO
Data Sheet
Figure 40 - Management Interface Timing for Ethernet Port - Write
11.7
External Memory Interface Timing
The timings for the External Memory Interface are based on the requirements of a ZBT-SRAM device, with the system clock speed at 100 MHz. Parameter RAM_DATA[63:0] Output Valid Delay RAM_RW/RAM_ADDR[19:0] Delay RAM_BW[7:0]# Delay RAM_DATA[63:0] Setup Time RAM_DATA[63:0] Hold Time RAM_PARITY[7:0] Output Valid Delay RAM_PARITY[7:0] Setup Time RAM_PARITY[7:0] Hold Time Symbol tRDV tRAV tRBW tRDS tRDH tRPV tRPS tRPS Min. 2 0.5 2 0.5 Typ. Max. 4 4 4 4 Units ns ns ns ns ns ns ns ns Load CL = 30 pF Notes Load CL = 30 pF Load CL = 30 pF Note 1 Load CL = 30 pF
Table 38 - External Memory Timing
Note 1: Must be capable of driving TWO separate RAM loads simultaneously.
n SCLK
Phase 1
Phase 2
Phase 3
Phase 4
Phase 5
Phase 6
Phase 7
Phase 8
tRAV RAM_ADDR[19:0]
A1 - READ A2 - WRITE A3 - WRITE A4 - READ A5 - READ A6 - WRITE A7 - READ A8 - WRITE A1 A2 A3 A4 A5 A6
tRAV
A7 A8
tRAV RAM_RW tRBW RAM_BW[7:0]
BW1 BW2 BW3 BW4 BW5 BW6
tRAV
BW7
BW8
tRDH tRDS
D(A1)
tRDH tRDV
Q(A2)
tRDS
Q(A3) D(A4) D(A5)
tRDV
Q(A6)
RAM_DATA[63:0] tRPS RAM_PARITY[7:0]
tRPH tRPV
P(A1) P(A2) P(A3) P(A4) P(A5)
tRPV
P(A6)
Figure 41 - External RAM Read and Write Timing
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11.8 CPU Interface Timing
Parameter CPU_CLK Period CPU_CLK High Time CPU_CLK Low Time CPU_CLK Rise Time CPU_CLK Fall Time CPU_ADDR[23:2] Setup Time CPU_ADDR[23:2] Hold Time CPU_DATA[31:0] Setup Time CPU_DATA[31:0] Hold Time CPU_CS Setup Time CPU_CS Hold Time CPU_WE/CPU_OE Setup Time CPU_WE/CPU_OE Hold Time CPU_TS_ALE Setup Time CPU_TS_ALE Hold Time CPU_SDACK1/CPU_SDACK2 Setup Time CPU_SDACK1/CPU_SDACK2 Hold Time CPU_TA Output Valid Delay CPU_DREQ0/CPU_DREQ1 Output Valid Delay CPU_IREQ0/CPU_IREQ1 Output Valid Delay CPU_DATA[31:0] Output Valid Delay CPU_CS to Output Data Valid CPU_OE to Output Data Valid CPU_CLK(falling) to CPU_TA Valid Symbol tCC tCCH tCCL tCCR tCCF tCAS tCAH tCDS tCDH tCSS tCSH tCES tCEH tCTS tCTH tCKS tCKH tCTV tCWV tCRV tCDV tSDV tODV tOTV 4 2 4 2 4 2 5 2 4 2 2 2 2 2 2 2 3.2 3.3 3.2 11.3 6 6 7 10.4 10.4 9.5 6 6 4 4 Min. Typ. 15.152 Max. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Data Sheet
Notes
Note 1 Note 1, 2 Note 1 Note 1 Note 1
Table 39 - CPU Timing Specification
Note 1: Note 2: Load = 50 pF maximum The maximum value of t CTV may cause setup violations if directly connected to the MPC8260. See Section 13.2 for details of how to accommodate this during board design.
The actual point where read/write data is transferred occurs at the positive clock edge following the assertion of CPU_TA, not at the positive clock edge during the assertion of CPU_TA.
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Data Sheet
tCC CPU_CLK tCAS CPU_ADDR[23:2] tCSS CPU_CS tCES CPU_OE CPU_WE tCTS CPU_TS_ALE tSDV CPU_DATA[31:0] tOTV CPU_TA tCTV tCTV tODV tCDV tCTH tCAH
0 or more cycles
tCSH tCEH
tODV tSDV
tOTV
NOTE: CPU_DATA is valid when CPU_TA is asserted. CPU_DATA will remain valid while both CPU_CS and CPU_OE are asserted. CPU_TA will continue to be driven until CPU_CS is deasserted. CPU_CS and CPU_OE must BOTH be asserted to enable the CPU_DATA output.
Figure 42 - CPU Read - MPC8260
tCC 0 or more cycles CPU_CLK tCAS CPU_ADDR[23:2] tCSS CPU_CS CPU_OE tCES CPU_WE tCTH tCTS CPU_TS_ALE tCDS CPU_DATA[31:0] tOTV CPU_TA tCTV tCTV tCDH tCEH tCAH
0 or more cycles
tCSH
tOTV
NOTE: Following assertion of CPU_TA, CPU_CS may be deasserted. The MPC8260 will continue to assert CPU_CS until CPU_TA has been synchronized internally. CPU_TA will continue to be driven until CPU_CS is finally deasserted. During continued assertion of CPU_CS, CPU_WE and CPU_DATA may be removed.
Figure 43 - CPU Write - MPC8260
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tCC CPU_CLK tCWV CPU_DREQ1 tCKS CPU_SDACK2 tCSS CPU_CS tCES CPU_OE CPU_WE tCTH tCTS CPU_TS_ALE tSDV CPU_DATA[31:0] tOTV CPU_TA tCTV tCTV tODV tCDV tODV tSDV tCEH tCSH tCKH tCWV
Data Sheet
0 or more cycles
tOTV
Note 1: CPU_SDACK2 must be asserted during the cycle shown. It may then be deasserted at any time. CPU_DATA is valid when CPU_TA is asserted (always timed as shown). CPU_DATA will remain valid while CPU_CS and CPU_OE are asserted. CPU_TA will continue to be driven until CPU_CS is deasserted. CPU_CS and CPU_OE must BOTH be asserted to enable
the CPU_DATA output. Note 2: CPU_DREQ1 shown with positive polarity CPU_SDACK1 shown with negative polarity
Figure 44 - CPU DMA Read - MPC8260
tCC CPU_CLK tCWV CPU_DREQ0 tCKS CPU_SDACK1 tCSS CPU_CS CPU_OE tCES CPU_WE tCTS CPU_TS_ALE tCDS CPU_DATA[31:0] tOTV CPU_TA tCTV tCTV tCDH tCTH tCEH tCKH tCWV
0 or more cycles
tCSH
tOTV
Note 1: CPU_SDACK1 must be asserted during the cycle shown. It may then be deasserted at any time. Following assertion of CPU_TA (always timed as shown), CPU_CS may be deasserted. The MPC8260 will continue to assert CPU_CS until CPU_TA has been synchronized internally. CPU_TA will continue to be driven until CPU_CS is finally deasserted. During continued assertion of CPU_CS, CPU_WE and CPU_DATA may be removed. Note 2: CPU_DREQ0 shown with positive polarity CPU_SDACK1 shown with negative polarity
Figure 45 - CPU DMA Write - MPC8260
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11.9 System Function Port
Parameter SYSTEM_CLK Frequency SYSTEM_CLK accuracy (synchronous master mode) SYSTEM_CLK accuracy (synchronous slave mode and asynchronous mode) Symbol CLKFR CLKACS CLKACA Min. Typ. 100 Max. 30 200 Units MHz ppm ppm
Data Sheet
Notes Note 1, Note 2 and Note 5 Note 3 Note 4
Table 40 - System Clock Timing
Note 1: The system clock frequency stability affects the holdover-operating mode of the DPLL. Holdover Mode is typically used for a short duration while network synchronisation is temporarily disrupted. Drift on the system clock directly affects the Holdover Mode accuracy. Note that the absolute system clock accuracy does not affect the Holdover accuracy, only the change in the system clock (SYSTEM_CLK) accuracy while in Holdover. For example, if the system clock oscillator has a temperature coefficient of 0.1 ppm/C, a 10C change in temperature while the DPLL is in will result in a frequency accuracy offset of 1ppm. The intrinsic frequency accuracy of the DPLL Holdover Mode is 0.06 ppm, excluding the system clock drift. The system clock frequency affects the operation of the DPLL in free-run mode. In this mode, the DPLL provides timing and synchronisation signals which are based on the frequency of the accuracy of the master clock (i.e. frequency of clock output equals 8.192 MHz SYSTEM_CLK accuracy 0.005 ppm). The absolute SYSTEM_CLK accuracy must be controlled to 30 ppm in synchronous master mode to enable the internal DPLL to function correctly. In asynchronous mode and in synchronous slave mode the DPLL is not used. Therefore the tolerance on SYSTEM_CLK may be relaxed slightly. The quality of SYSTEM_CLK, or the oscillator that drives SYSTEM_CLK directly impacts the adaptive clock recovery performance. See Section 6.3.
Note 2:
Note 3: Note 4: Note 5:
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11.10 JTAG Interface Timing
Parameter JTAG_CLK period JTAG_CLK clock pulse width JTAG_CLK rise and fall time JTAG_TRST setup time Symbol tJCP tLOW, tHIGH tJRF tRSTSU Min. 40 20 0 10 Typ. 100 3 Max. Units ns ns ns ns
Data Sheet
Notes
With respect to JTAG_CLK falling edge. Note 1 Note 2 Note 2 Note 3 Note 3
JTAG_TRST assert time Input data setup time Input Data hold time JTAG_CLK to Output data valid JTAG_CLK to Output data high impedance JTAG_TMS, JTAG_TDI setup time JTAG_TMS, JTAG_TDI hold time JTAG_TDO delay JTAG_TDO delay to high impedance
tRST tJSU tJH tJDV tJZ tTPSU tTPH tTOPDV tTPZ
10 5 15 0 0 5 15 0 0
-
20 20 15 15
ns ns ns ns ns ns ns ns ns
Table 41 - JTAG Interface Timing
Note 1: Note 2: Note 3: JTAG_TRST is an asynchronous signal. The setup time is for test purposes only. Non Test (other than JTAG_TDI and JTAG_TMS) signal input timing with respect to JTAG_CLK. Non Test (other than JTAG_TDO) signal output with respect to JTAG_CLK.
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Data Sheet
tLOW tHIGH JTAG_TCK tTPH tTPSU JTAG_TMS tTPSU JTAG_TDI Don't Care tTOPDV JTAG_TDO HiZ tTPZ HiZ tTPH DC tJCP
Figure 46 - JTAG Signal Timing
tLOW JTAG_TCK tRST JTAG_TRST
tHIGH
tRSTSU
Figure 47 - JTAG Clock and Reset Timing
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12.0 Power Characteristics
Data Sheet
The following graph in Figure 48 illustrates typical power consumption figures for the ZL50110/11/14 family. Typical characteristics are at 1.8V core, 3.3V I/O, 25C and typical processing. Power is plotted against the number of active contexts, which is the dominant factor for power consumption.
ZL501x Power Consumption (Typical Conditions)
2 1.8 1.6 1.4 Power (W) 1.2 1 0.8 0.6 0.4 0.2 0 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 Number of Active Contexts
Figure 48 - ZL50110/11/14 Power Consumption Plot
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13.0 Design and Layout Guidelines
Data Sheet
This guide will provide information and guidance for PCB layouts when using the ZL50110/11/14. Specific areas of guidance are: * * High Speed Clock and Data, Outputs and Inputs CPU_TA Output
13.1
High Speed Clock & Data Interfaces
On the ZL50110/11/14 series of devices there are four high-speed data interfaces that need consideration when laying out a PCB to ensure correct termination of traces and the reduction of crosstalk noise. The interfaces being: * * * * External Memory Interface GMAC Interfaces TDM Interface CPU Interface
It is recommended that the outputs are suitably terminated using a series termination through a resistor as close to the output pin as possible. The purpose of the series termination resistor is to reduce reflections on the line. The value of the series termination and the length of trace the output can drive will depend on the driver output impedance, the characteristic impedance of the PCB trace (recommend 50 ohm), the distributed trace capacitance and the load capacitance. As a general rule of thumb, if the trace length is less than 1/6th of the equivalent length of the rise and fall times, then a series termination may not be required. the equivalent length of rise time = rise time (ps) / delay (ps/mm) For example: Typical FR4 board delay = 6.8 ps/mm Typical rise/fall time for a ZL50110/11/14 output = 2.5 ns critical track length = (1/6) x (2500/6.8) = 61 mm Therefore tracks longer than 61 mm will require termination. As a signal travels along a trace it creates a magnetic field, which induces noise voltages in adjacent traces, this is crosstalk. If the crosstalk is of sufficiently strong amplitude, false data can be induced in the trace and therefore it should be minimised in the layout. The voltage that the external fields cause is proportional to the strength of the field and the length of the trace exposed to the field. Therefore to minimise the effect of crosstalk some basic guidelines should be followed. First, increase separation of sensitive signals, a rough rule of thumb is that doubling the separation reduces the coupling by a factor of four. Alternatively, shield the victim traces from the aggressor by either routing on another layer separated by a power plane (in a correctly decoupled design the power planes have the same AC potential) or by placing guard traces between the signals usually held ground potential. Particular effort should be made to minimise crosstalk from ZL50110/11/14 outputs and ensuring fast rise time to these inputs. In Summary: * * * * Place series termination resistors as close to the pins as possible Minimise output capacitance Keep common interface traces close to the same length to avoid skew Protect input clocks and signals from crosstalk
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13.1.1 External Memory Interface - special considerations during layout
Data Sheet
The timing of address, data and control are all related to the system clock which is also used by the external SSRAM to clock these signals. Therefore the propagation delay of the clock to the ZL50110/11/14 and the SSRAM must be matched to within 250 ps, worst case conditions. Trace lengths of theses signals must also be minimized (<100 mm) and matched to ensure correct operation under all conditions.
13.1.2
GMAC Interface - special considerations during layout
The GMII interface passes data to and from the ZL50110/11/14 with their related transmit and receive clocks. It is therefore recommended that the trace lengths for transmit related signals and their clock and the receive related signals and their clock are kept to the same length. By doing this the skew between individual signals and their related clock will be minimized.
13.1.3
TDM Interface - special considerations during layout
Although the data rate of this interface is low the outputs edge speeds share the characteristics of the higher data rate outputs and therefore must be treated with the same care extended to the other interfaces with particular reference to the lower stream numbers which support the higher data rates. The TDM interface has numerous clocking schemes and as a result of this the input clock traces to the ZL50110/11/14 devices should be treated with care.
13.1.4
Summary
Particular effort should be made to minimise crosstalk from ZL50110/11/14 outputs and ensuring fast rise time to these inputs. In Summary: * * * * Place series termination resistors as close to the pins as possible Minimise output capacitance Keep common interface traces close to the same length to avoid skew Protect input clocks and signals from crosstalk
13.2
CPU TA Output
The CPU_TA output signal from the ZL50110/11/14 is a critical handshake signal to the CPU that ensures the correct completion of a bus transaction between the two devices. As the signal is critical, it is recommend that the circuit shown in Figure 49 is implemented in systems operating above 40 MHz bus frequency to ensure robust operation under all conditions. The following external logic is required to implement the circuit: * * * * 74LCX74 dual D-type flip-flop (one section of two) 74LCX08 quad AND gate (one section of four) 74LCX125 quad tri-state buffer (one section of four) 4K7 resistor x2
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Data Sheet
+3V3
+3V3
R1 4K7
R2 4K7
CPU_TA from ZL50110/11/14
CPU_TA to CPU
D
Q
CPU_CLK to ZL50110/11/14
CPU_CS to ZL50110/11/14
Figure 49 - CPU_TA Board Circuit The function of the circuit is to extend the TA signal, to ensure the CPU correctly registers it. Resistor R2 must be fitted to ensure correct operation of the TA input to the processor. It is recommended that the logic is fitted close to the ZL50110/11/14 and that the clock to the 74LCX74 is derived from the same clock source as that input to the ZL50110/11/14.
13.3
Mx_LINKUP_LED Outputs
The ZL50111 and ZL50110/1/4 have different Mx_LINKUP_LED pin assignments as shown in Table 42. Signal M0_LINKUP_LED M1_LINKUP_LED M2_LINKUP_LED M3_LINKUP_LED ZL50111 Pin AB23 F26 G23 G24 ZL50110/4 Pin G24 G23 NC NC
Table 42 - Mx_LINKUP_LED Pin Assignments
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Data Sheet
To generate a pin for pin compatible PCB for all three variants, the following stuffing options may be used as shown in Figure 50. For the ZL50111 variant, resistors R4 and R6 are not populated. For the ZL50110 and ZL50114 variants, resistors R1, R2, R3 and R5 as well as LEDs for M2 and M3 are not populated.
VDD_IO
M0_LINKUP_LED
M0_LINKUP_LED (AB23)
R1
VDD_IO
M1_LINKUP_LED
M1_LINKUP_LED (F26)
R2
VDD_IO
ZL50110/1/4
M2_LINKUP_LED
M1/2_LINKUP_LED (G23)
R3 R4
VDD_IO
M3_LINKUP_LED
M0/3_LINKUP_LED (G24)
R5 R6
Figure 50 - Mx_LINKUP_LED Stuffing Option
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Table 43 lists the various components that are used for each variant.
Component ZL50111 ZL50110/4
Data Sheet
R1 R2 R3 R4 R5 R6 M0 LED M1 LED M2 LED M3 LED

Table 43 - Mx_LINKUP_LED Stuffing Option
-
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14.0
14.1
* * * * * * * * * * * * * * * * * * * * * * * *
Data Sheet
Reference Documents
External Standards/Specifications
IEEE Standard 1149.1-2001; Test Access Port and Boundary Scan Architecture IEEE Standard 802.3-2000; Local and Metropolitan Networks CSMA/CD Access Method and Physical Layer ECTF H.110 Revision 1.0; Hardware Compatibility Specification H-MVIP (GO-MVIP) Standard Release 1.1a; Multi-Vendor Integration Protocol MPC8260AEC/D Revision 0.7; Motorola MPC8260 Family Hardware Specification RFC 768; UDP RFC 791; IPv4 RFC2460; IPv6 RFC 1889; RTP RFC 2661; L2TP RFC 1213; MIB II RFC 1757; Remote Network Monitoring MIB (for SMIv1) RFC 2819; Remote Network Monitoring MIB (for SMIv2) RFC 2863; Interfaces Group MIB CCITT G.712; TDM Timing Specification (Method 2) G.823; Control of Jitter/Wander with digital networks based on the 2.048 Mbps hierarchy G.824; Control of Jitter/Wander with digital networks based on the 1.544 Mbps hierarchy ANSI T1.101 Stratum 3/4 Telcordia GR-1244-CORE Stratum 3/4/4e IETF PWE3 draft-ietf-l2tpext-l2tp-base IETF PWE3 draft-ietf-pwe3-cesopsn IETF PWE3 draft-ietf-pwe3-satop ITU-T Y.1413 TDM-MPLS Network Interworking
Optional Packet Memory Device - Micron MT55L128L32P1 8 Mb ZBT-SRAM
14.2
*
Zarlink Standards
MSAN-126 Revision B, Issue 4; ST-BUS Generic Device Specification
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15.0
API ATM CDP CESoP
Data Sheet
Glossary
Application Program Interface Asynchronous Transfer Mode Context Descriptor Protocol (the protocol used by Zarlink's MT9088x family of TDM-Packet devices) Circuit Emulation Services over Packet
CESoPSN Circuit Emulation Services over Packet Switched Networks (draft-ietf-pwe3-cesopsn) CONTEXT A programmed connection of a number of TDM timeslots assembled into a unique packet stream. CPU DMA DPLL DSP GMII
Central Processing Unit Direct Memory Access Digital Phase Locked Loop Digital Signal Processor Gigabit Media Independent Interface
H.100/H.110High capacity TDM backplane standards H-MVIP IA IETF IP JTAG L2TP LAN LIU MAC MEF MFA MII MIB MPLS MTIE MVIP OC3 PDH PLL PRS PRX
High-performance Multi-Vendor Integration Protocol (a TDM bus standard) Implementation Agreement Internet Engineering Task Force Internet Protocol (version 4, RFC 791, version 6, RFC 2460) Joint Test Algorithms Group (generally used to refer to a standard way of providing a board-level test facility) Layer 2 Tunneling Protocol (RFC 2661) Local Area Network Line Interface Unit Media Access Control Metro Ethernet Forum MPLS and Frame Relay Alliance Media Independent Interface Management Information Base Multi Protocol Label Switching Maximum Time Interval Error Multi-Vendor Integration Protocol (a TDM bus standard) Optical Carrier 3 - 155.52 Mbps leased line Plesiochronous Digital Hierarchy Phase Locked Loop Primary Reference Source Packet Receive
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ZL50110/11/14
PSTN PTX PWE3 QOS RTP PE SAToP SSRAM ST BUS TDL TDM UDP UI VLAN WFQ ZBT
Data Sheet
Public Switched Telephone Circuit Packet Transmit Pseudo-Wire Emulation Edge to Edge (a working group of the IETF) Quality of Service Real Time Protocol (RFC 1889) Protocol Engine Structure-Agnostic Transport over Packet Synchronous Static Random Access Memory Standard Telecom Bus, a standard interface for TDM data streams Tapped Delay Line Time Division Multiplexing User Datagram Protocol (RFC 768) Unit Interval Virtual Local Area Network Weighted Fair Queuing Zero Bus Turnaround, a type of synchronous SRAM
101
Zarlink Semiconductor Inc.
c Zarlink Semiconductor 2003 All rights reserved.
Package Code Previous package codes
ISSUE ACN DATE APPRD.
1 213837 12Dec02
2
19Aug03
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